From: Cornelia Huck <cohuck@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-s390x@nongnu.org, Cornelia Huck <cohuck@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, David Hildenbrand <david@redhat.com>
Subject: [PULL 06/37] s390x/tcg: Simplify vfc64() handling
Date: Mon, 21 Jun 2021 11:58:11 +0200 [thread overview]
Message-ID: <20210621095842.335162-7-cohuck@redhat.com> (raw)
In-Reply-To: <20210621095842.335162-1-cohuck@redhat.com>
From: David Hildenbrand <david@redhat.com>
Pass the m5 field via simd_data() and don't provide specialized handlers
for single-element variants.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-6-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/s390x/helper.h | 6 ---
target/s390x/translate_vx.c.inc | 45 +++++-----------
target/s390x/vec_fpu_helper.c | 94 +++++++++------------------------
3 files changed, 38 insertions(+), 107 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 4788c1ddaf8c..02a16924a7b7 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -250,17 +250,11 @@ DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_FLAGS_5(gvec_vfce64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfce64_cc, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_5(gvec_vfce64s_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfch64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_FLAGS_5(gvec_vfch64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfch64_cc, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_5(gvec_vfch64s_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_FLAGS_5(gvec_vfche64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index 280d45bb196f..604ae11024a9 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2497,7 +2497,6 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
const uint8_t fpf = get_field(s, m4);
const uint8_t m5 = get_field(s, m5);
const uint8_t m6 = get_field(s, m6);
- const bool se = extract32(m5, 3, 1);
const bool cs = extract32(m6, 0, 1);
gen_helper_gvec_3_ptr *fn;
@@ -2506,37 +2505,21 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- if (cs) {
- switch (s->fields.op2) {
- case 0xe8:
- fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc;
- break;
- case 0xeb:
- fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc;
- break;
- case 0xea:
- fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc;
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- switch (s->fields.op2) {
- case 0xe8:
- fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64;
- break;
- case 0xeb:
- fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64;
- break;
- case 0xea:
- fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64;
- break;
- default:
- g_assert_not_reached();
- }
+ switch (s->fields.op2) {
+ case 0xe8:
+ fn = cs ? gen_helper_gvec_vfce64_cc : gen_helper_gvec_vfce64;
+ break;
+ case 0xeb:
+ fn = cs ? gen_helper_gvec_vfch64_cc : gen_helper_gvec_vfch64;
+ break;
+ case 0xea:
+ fn = cs ? gen_helper_gvec_vfche64_cc : gen_helper_gvec_vfche64;
+ break;
+ default:
+ g_assert_not_reached();
}
- gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, 0, fn);
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3),
+ cpu_env, m5, fn);
if (cs) {
set_cc_static(s);
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index ab23a597da73..01ee41d1543c 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -239,8 +239,8 @@ static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
int i;
for (i = 0; i < 2; i++) {
- const float64 a = s390_vec_read_element64(v2, i);
- const float64 b = s390_vec_read_element64(v3, i);
+ const float64 a = s390_vec_read_float64(v2, i);
+ const float64 b = s390_vec_read_float64(v3, i);
/* swap the order of the parameters, so we can use existing functions */
if (fn(b, a, &env->fpu_status)) {
@@ -261,77 +261,31 @@ static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
return 3;
}
-void HELPER(gvec_vfce64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
-}
-
-void HELPER(gvec_vfce64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
-}
-
-void HELPER(gvec_vfce64_cc)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- env->cc_op = vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
-}
-
-void HELPER(gvec_vfce64s_cc)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- env->cc_op = vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
-}
-
-void HELPER(gvec_vfch64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
-}
-
-void HELPER(gvec_vfch64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
-}
-
-void HELPER(gvec_vfch64_cc)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- env->cc_op = vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
-}
-
-void HELPER(gvec_vfch64s_cc)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- env->cc_op = vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
-}
-
-void HELPER(gvec_vfche64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
-}
-
-void HELPER(gvec_vfche64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
+#define DEF_GVEC_VFC_B(NAME, OP, BITS) \
+void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2, const void *v3, \
+ CPUS390XState *env, uint32_t desc) \
+{ \
+ const bool se = extract32(simd_data(desc), 3, 1); \
+ vfc##BITS##_fn fn = float##BITS##_##OP##_quiet; \
+ \
+ vfc##BITS(v1, v2, v3, env, se, fn, GETPC()); \
+} \
+ \
+void HELPER(gvec_##NAME##BITS##_cc)(void *v1, const void *v2, const void *v3, \
+ CPUS390XState *env, uint32_t desc) \
+{ \
+ const bool se = extract32(simd_data(desc), 3, 1); \
+ vfc##BITS##_fn fn = float##BITS##_##OP##_quiet; \
+ \
+ env->cc_op = vfc##BITS(v1, v2, v3, env, se, fn, GETPC()); \
}
-void HELPER(gvec_vfche64_cc)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- env->cc_op = vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
-}
+#define DEF_GVEC_VFC(NAME, OP) \
+DEF_GVEC_VFC_B(NAME, OP, 64)
-void HELPER(gvec_vfche64s_cc)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- env->cc_op = vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
-}
+DEF_GVEC_VFC(vfce, eq)
+DEF_GVEC_VFC(vfch, lt)
+DEF_GVEC_VFC(vfche, le)
static void vfll32(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
bool s, uintptr_t retaddr)
--
2.31.1
next prev parent reply other threads:[~2021-06-21 10:04 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-21 9:58 [PULL 00/37] s390x update Cornelia Huck
2021-06-21 9:58 ` [PULL 01/37] s390x/kvm: remove unused gs handling Cornelia Huck
2021-06-21 9:58 ` [PULL 02/37] s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handling Cornelia Huck
2021-06-21 9:58 ` [PULL 03/37] s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED) Cornelia Huck
2021-06-21 9:58 ` [PULL 04/37] s390x/tcg: Simplify vop64_3() handling Cornelia Huck
2021-06-21 9:58 ` [PULL 05/37] s390x/tcg: Simplify vop64_2() handling Cornelia Huck
2021-06-21 9:58 ` Cornelia Huck [this message]
2021-06-21 9:58 ` [PULL 07/37] s390x/tcg: Simplify vftci64() handling Cornelia Huck
2021-06-21 9:58 ` [PULL 08/37] s390x/tcg: Simplify vfma64() handling Cornelia Huck
2021-06-21 9:58 ` [PULL 09/37] s390x/tcg: Simplify vfll32() handling Cornelia Huck
2021-06-21 9:58 ` [PULL 10/37] s390x/tcg: Simplify vflr64() handling Cornelia Huck
2021-06-21 9:58 ` [PULL 11/37] s390x/tcg: Simplify wfc64() handling Cornelia Huck
2021-06-21 9:58 ` [PULL 12/37] s390x/tcg: Implement VECTOR BIT PERMUTE Cornelia Huck
2021-06-21 9:58 ` [PULL 13/37] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL Cornelia Huck
2021-06-21 9:58 ` [PULL 14/37] s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT) Cornelia Huck
2021-06-21 9:58 ` [PULL 15/37] s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT) Cornelia Huck
2021-06-21 9:58 ` [PULL 16/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE * Cornelia Huck
2021-06-21 9:58 ` [PULL 17/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR Cornelia Huck
2021-06-21 9:58 ` [PULL 18/37] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED Cornelia Huck
2021-06-21 9:58 ` [PULL 19/37] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED Cornelia Huck
2021-06-21 9:58 ` [PULL 20/37] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION Cornelia Huck
2021-06-21 9:58 ` [PULL 21/37] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE Cornelia Huck
2021-06-21 9:58 ` [PULL 22/37] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT) Cornelia Huck
2021-06-21 9:58 ` [PULL 23/37] s390x/tcg: Implement VECTOR FP NEGATIVE " Cornelia Huck
2021-06-21 9:58 ` [PULL 24/37] s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM) Cornelia Huck
2021-06-21 9:58 ` [PULL 25/37] linux-user: elf: s390x: Prepare for Vector enhancements facility Cornelia Huck
2021-06-21 9:58 ` [PULL 26/37] s390x/tcg: We support " Cornelia Huck
2021-06-21 9:58 ` [PULL 27/37] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2 Cornelia Huck
2021-06-21 9:58 ` [PULL 28/37] configure: Check whether we can compile the s390-ccw bios with -msoft-float Cornelia Huck
2021-06-21 9:58 ` [PULL 29/37] target/s390x: Expose load_psw and get_psw_mask to cpu.h Cornelia Huck
2021-06-21 9:58 ` [PULL 30/37] target/s390x: Do not modify cpu state in s390_cpu_get_psw_mask Cornelia Huck
2021-06-21 9:58 ` [PULL 31/37] target/s390x: Improve s390_cpu_dump_state vs cc_op Cornelia Huck
2021-06-21 9:58 ` [PULL 32/37] target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub Cornelia Huck
2021-06-21 9:58 ` [PULL 33/37] linux-user/s390x: Save and restore psw.mask properly Cornelia Huck
2021-06-21 9:58 ` [PULL 34/37] s390x/css: Introduce an ESW struct Cornelia Huck
2021-06-21 9:58 ` [PULL 35/37] s390x/css: Split out the IRB sense data Cornelia Huck
2021-06-21 9:58 ` [PULL 36/37] s390x/css: Refactor IRB construction Cornelia Huck
2021-06-21 9:58 ` [PULL 37/37] s390x/css: Add passthrough IRB Cornelia Huck
2021-06-21 10:39 ` [PULL 00/37] s390x update no-reply
2021-06-22 15:07 ` Peter Maydell
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