From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: qemu-devel@nongnu.org
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Subject: [PATCH 3/3] hw/sh4: sh7750 switch renesas_timer.
Date: Wed, 23 Jun 2021 21:34:16 +0900 [thread overview]
Message-ID: <20210623123416.60038-4-ysato@users.sourceforge.jp> (raw)
In-Reply-To: <20210623123416.60038-1-ysato@users.sourceforge.jp>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
hw/sh4/sh7750.c | 32 +++++++++++++++++++++++++++++---
hw/sh4/Kconfig | 2 +-
2 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index d53a436d8c..bbebac8083 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -30,8 +30,10 @@
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
#include "hw/sh4/sh_intc.h"
-#include "hw/timer/tmu012.h"
+#include "hw/timer/renesas_timer.h"
#include "exec/exec-all.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
#define NB_DEVICES 4
@@ -752,6 +754,30 @@ static const MemoryRegionOps sh7750_mmct_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void tmu012_init(MemoryRegion *sysmem, hwaddr base,
+ int unit, uint64_t freq,
+ qemu_irq ch0_irq, qemu_irq ch1_irq,
+ qemu_irq ch2_irq0, qemu_irq ch2_irq1)
+{
+ RenesasTMUState *tmu;
+
+ tmu = RENESAS_TMU(qdev_new(TYPE_RENESAS_TMU));
+ qdev_prop_set_uint32(DEVICE(tmu), "unit", unit);
+ qdev_prop_set_uint64(DEVICE(tmu), "input-freq", freq);
+
+ sysbus_realize(SYS_BUS_DEVICE(tmu), &error_abort);
+ sysbus_connect_irq(SYS_BUS_DEVICE(tmu), 0, ch0_irq);
+ sysbus_connect_irq(SYS_BUS_DEVICE(tmu), 1, ch1_irq);
+ if (unit == 0) {
+ /* ch2_irq1 is not used. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(tmu), 2, ch2_irq0);
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(tmu), 0, base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(tmu), 1, P4ADDR(base));
+ sysbus_mmio_map(SYS_BUS_DEVICE(tmu), 2, A7ADDR(base));
+}
+
SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
{
SH7750State *s;
@@ -817,7 +843,7 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
s->intc.irqs[SCIF_BRI]);
tmu012_init(sysmem, 0x1fd80000,
- TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
+ 0,
s->periph_freq,
s->intc.irqs[TMU0],
s->intc.irqs[TMU1],
@@ -840,7 +866,7 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34),
NULL, 0);
- tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
+ tmu012_init(sysmem, 0x1e100000, 1, s->periph_freq,
s->intc.irqs[TMU3],
s->intc.irqs[TMU4],
NULL, NULL);
diff --git a/hw/sh4/Kconfig b/hw/sh4/Kconfig
index ab733a3f76..ee51b5e6ae 100644
--- a/hw/sh4/Kconfig
+++ b/hw/sh4/Kconfig
@@ -21,4 +21,4 @@ config SH7750
bool
select SH_INTC
select SH_SCI
- select SH_TIMER
+ select RENESAS_TIMER
--
2.20.1
prev parent reply other threads:[~2021-06-23 12:39 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-23 12:34 [PATCH 0/3] Integrate renesas MCU/SoC timer module Yoshinori Sato
2021-06-23 12:34 ` [PATCH 1/3] hw/timer: Add renesas_timer Yoshinori Sato
2021-06-24 8:43 ` Philippe Mathieu-Daudé
2021-06-23 12:34 ` [PATCH 2/3] hw/rx: rx62n switch renesas_timer Yoshinori Sato
2021-06-24 9:01 ` Philippe Mathieu-Daudé
2021-06-23 12:34 ` Yoshinori Sato [this message]
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