From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64}
Date: Fri, 25 Jun 2021 23:36:05 -0700 [thread overview]
Message-ID: <20210626063631.2411938-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210626063631.2411938-1-richard.henderson@linaro.org>
Pass in the input and output size. We currently use 3 of the 5
possible combinations; the others may be used by new tcg opcodes.
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 42 ++++++++++++++----------------------
1 file changed, 16 insertions(+), 26 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 27cde314a9..8619e54fca 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -475,9 +475,7 @@ typedef enum {
/* Data-processing (1 source) instructions. */
I3507_CLZ = 0x5ac01000,
I3507_RBIT = 0x5ac00000,
- I3507_REV16 = 0x5ac00400,
- I3507_REV32 = 0x5ac00800,
- I3507_REV64 = 0x5ac00c00,
+ I3507_REV = 0x5ac00000, /* + size << 10 */
/* Data-processing (2 source) instructions. */
I3508_LSLV = 0x1ac02000,
@@ -1417,19 +1415,11 @@ static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a,
}
}
-static inline void tcg_out_rev64(TCGContext *s, TCGReg rd, TCGReg rn)
+static inline void tcg_out_rev(TCGContext *s, int ext, MemOp s_bits,
+ TCGReg rd, TCGReg rn)
{
- tcg_out_insn(s, 3507, REV64, TCG_TYPE_I64, rd, rn);
-}
-
-static inline void tcg_out_rev32(TCGContext *s, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3507, REV32, TCG_TYPE_I32, rd, rn);
-}
-
-static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn);
+ /* REV, REV16, REV32 */
+ tcg_out_insn_3507(s, I3507_REV | (s_bits << 10), ext, rd, rn);
}
static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,
@@ -1737,13 +1727,13 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
case MO_UW:
tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
if (bswap) {
- tcg_out_rev16(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, data_r, data_r);
}
break;
case MO_SW:
if (bswap) {
tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
- tcg_out_rev16(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, data_r, data_r);
tcg_out_sxt(s, ext, MO_16, data_r, data_r);
} else {
tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
@@ -1753,13 +1743,13 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
case MO_UL:
tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
if (bswap) {
- tcg_out_rev32(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, data_r, data_r);
}
break;
case MO_SL:
if (bswap) {
tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
- tcg_out_rev32(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, data_r, data_r);
tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);
} else {
tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
@@ -1768,7 +1758,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
case MO_Q:
tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
if (bswap) {
- tcg_out_rev64(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I64, MO_64, data_r, data_r);
}
break;
default:
@@ -1788,21 +1778,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
break;
case MO_16:
if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev16(s, TCG_REG_TMP, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
break;
case MO_32:
if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev32(s, TCG_REG_TMP, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
break;
case MO_64:
if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev64(s, TCG_REG_TMP, data_r);
+ tcg_out_rev(s, TCG_TYPE_I64, MO_64, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
@@ -2184,15 +2174,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_bswap64_i64:
- tcg_out_rev64(s, a0, a1);
+ tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
break;
case INDEX_op_bswap32_i64:
case INDEX_op_bswap32_i32:
- tcg_out_rev32(s, a0, a1);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
break;
case INDEX_op_bswap16_i64:
case INDEX_op_bswap16_i32:
- tcg_out_rev16(s, a0, a1);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, a0, a1);
break;
case INDEX_op_ext8s_i64:
--
2.25.1
next prev parent reply other threads:[~2021-06-26 6:37 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
2021-06-26 6:36 ` [PATCH v3 01/29] tcg: Add flags argument to bswap opcodes Richard Henderson
2021-06-26 6:36 ` [PATCH v3 02/29] tcg/i386: Support bswap flags Richard Henderson
2021-06-26 6:36 ` Richard Henderson [this message]
2021-06-28 14:16 ` [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64} Peter Maydell
2021-06-26 6:36 ` [PATCH v3 04/29] tcg/aarch64: Support bswap flags Richard Henderson
2021-06-26 9:38 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 05/29] tcg/arm: " Richard Henderson
2021-06-26 6:36 ` [PATCH v3 06/29] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
2021-06-26 6:36 ` [PATCH v3 07/29] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
2021-06-26 6:36 ` [PATCH v3 08/29] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 09/29] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 10/29] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 11/29] tcg/ppc: Support bswap flags Richard Henderson
2021-06-26 9:32 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
2021-06-28 14:33 ` Peter Maydell
2021-06-28 14:45 ` Richard Henderson
2021-06-28 16:22 ` Bruno Piazera Larsen
2021-06-26 6:36 ` [PATCH v3 13/29] tcg/s390: Support bswap flags Richard Henderson
2021-06-28 14:43 ` Peter Maydell
2021-06-28 14:50 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
2021-06-26 9:30 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 16/29] tcg/tci: Support bswap flags Richard Henderson
2021-06-26 6:36 ` [PATCH v3 17/29] tcg: Handle new bswap flags during optimize Richard Henderson
2021-06-26 6:36 ` [PATCH v3 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
2021-06-26 6:36 ` [PATCH v3 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
2021-06-26 6:36 ` [PATCH v3 21/29] target/arm: Improve REV32 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 22/29] target/arm: Improve vector REV Richard Henderson
2021-06-26 6:36 ` [PATCH v3 23/29] target/arm: Improve REVSH Richard Henderson
2021-06-26 6:36 ` [PATCH v3 24/29] target/i386: Improve bswap translation Richard Henderson
2021-06-26 6:36 ` [PATCH v3 25/29] target/sh4: Improve swap.b translation Richard Henderson
2021-06-26 6:36 ` [PATCH v3 26/29] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
2021-06-26 6:36 ` [PATCH v3 27/29] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Richard Henderson
2021-06-26 6:36 ` [PATCH v3 28/29] tcg/aarch64: " Richard Henderson
2021-06-26 6:36 ` [PATCH v3 29/29] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
2021-06-26 7:03 ` [PATCH v3 00/29] tcg: bswap improvements no-reply
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