From: <hnick@vmware.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Nick Hudson <hnick@vmware.com>,
"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
Mohannad Ismail <imohannad@vmware.com>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Subject: [PATCH] target/arm: Correct the encoding of MDCCSR_EL0
Date: Tue, 29 Jun 2021 09:27:13 +0100 [thread overview]
Message-ID: <20210629082713.31396-1-hnick@vmware.com> (raw)
Signed-off-by: Nick Hudson <hnick@vmware.com>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a66c1f0b9e..7267af7924 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6330,7 +6330,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
* We don't implement the configurable EL0 access.
*/
{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
+ .cp = 14, .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
.type = ARM_CP_ALIAS,
.access = PL1_R, .accessfn = access_tda,
.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
--
2.17.1
next reply other threads:[~2021-06-29 13:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-29 8:27 hnick [this message]
2021-06-29 9:49 ` [PATCH] target/arm: Correct the encoding of MDCCSR_EL0 Peter Maydell
2021-06-29 10:41 ` Nick Hudson
2021-06-29 11:50 ` Peter Maydell
2021-07-02 15:01 ` Nick Hudson
2021-07-05 12:51 ` Peter Maydell
2021-07-02 15:01 ` Nick Hudson
-- strict thread matches above, loose matches on Subject: below --
2021-06-29 8:15 Nick Hudson
2021-06-29 14:00 ` Richard Henderson
2021-06-29 14:12 ` Peter Maydell
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