From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Michael Rolnik" <mrolnik@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 11/63] target/avr: Change ctx to DisasContext* in gen_intermediate_code
Date: Tue, 29 Jun 2021 11:54:03 -0700 [thread overview]
Message-ID: <20210629185455.3131172-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210629185455.3131172-1-richard.henderson@linaro.org>
Prepare for receiving it as a pointer input.
Tested-by: Michael Rolnik <mrolnik@gmail.com>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/translate.c | 84 +++++++++++++++++++++---------------------
1 file changed, 43 insertions(+), 41 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 20c5062730..66e9882422 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -104,7 +104,7 @@ struct DisasContext {
* used in the following manner (sketch)
*
* TCGLabel *skip_label = NULL;
- * if (ctx.skip_cond != TCG_COND_NEVER) {
+ * if (ctx->skip_cond != TCG_COND_NEVER) {
* skip_label = gen_new_label();
* tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label);
* }
@@ -114,7 +114,7 @@ struct DisasContext {
* free_skip_var0 = false;
* }
*
- * translate(&ctx);
+ * translate(ctx);
*
* if (skip_label) {
* gen_set_label(skip_label);
@@ -2900,7 +2900,7 @@ static bool canonicalize_skip(DisasContext *ctx)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
CPUAVRState *env = cs->env_ptr;
- DisasContext ctx = {
+ DisasContext ctx1 = {
.base.tb = tb,
.base.is_jmp = DISAS_NEXT,
.base.pc_first = tb->pc,
@@ -2911,6 +2911,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
.memidx = 0,
.skip_cond = TCG_COND_NEVER,
};
+ DisasContext *ctx = &ctx1;
target_ulong pc_start = tb->pc / 2;
int num_insns = 0;
@@ -2921,23 +2922,23 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
*/
max_insns = 1;
}
- if (ctx.base.singlestep_enabled) {
+ if (ctx->base.singlestep_enabled) {
max_insns = 1;
}
gen_tb_start(tb);
- ctx.npc = pc_start;
+ ctx->npc = pc_start;
if (tb->flags & TB_FLAGS_SKIP) {
- ctx.skip_cond = TCG_COND_ALWAYS;
- ctx.skip_var0 = cpu_skip;
+ ctx->skip_cond = TCG_COND_ALWAYS;
+ ctx->skip_var0 = cpu_skip;
}
do {
TCGLabel *skip_label = NULL;
/* translate current instruction */
- tcg_gen_insn_start(ctx.npc);
+ tcg_gen_insn_start(ctx->npc);
num_insns++;
/*
@@ -2946,65 +2947,66 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
* b main - sets breakpoint at address 0x00000100 (code)
* b *0x100 - sets breakpoint at address 0x00800100 (data)
*/
- if (unlikely(!ctx.base.singlestep_enabled &&
- (cpu_breakpoint_test(cs, OFFSET_CODE + ctx.npc * 2, BP_ANY) ||
- cpu_breakpoint_test(cs, OFFSET_DATA + ctx.npc * 2, BP_ANY)))) {
- canonicalize_skip(&ctx);
- tcg_gen_movi_tl(cpu_pc, ctx.npc);
+ if (unlikely(!ctx->base.singlestep_enabled &&
+ (cpu_breakpoint_test(cs, OFFSET_CODE + ctx->npc * 2, BP_ANY) ||
+ cpu_breakpoint_test(cs, OFFSET_DATA + ctx->npc * 2, BP_ANY)))) {
+ canonicalize_skip(ctx);
+ tcg_gen_movi_tl(cpu_pc, ctx->npc);
gen_helper_debug(cpu_env);
goto done_generating;
}
/* Conditionally skip the next instruction, if indicated. */
- if (ctx.skip_cond != TCG_COND_NEVER) {
+ if (ctx->skip_cond != TCG_COND_NEVER) {
skip_label = gen_new_label();
- if (ctx.skip_var0 == cpu_skip) {
+ if (ctx->skip_var0 == cpu_skip) {
/*
* Copy cpu_skip so that we may zero it before the branch.
* This ensures that cpu_skip is non-zero after the label
* if and only if the skipped insn itself sets a skip.
*/
- ctx.free_skip_var0 = true;
- ctx.skip_var0 = tcg_temp_new();
- tcg_gen_mov_tl(ctx.skip_var0, cpu_skip);
+ ctx->free_skip_var0 = true;
+ ctx->skip_var0 = tcg_temp_new();
+ tcg_gen_mov_tl(ctx->skip_var0, cpu_skip);
tcg_gen_movi_tl(cpu_skip, 0);
}
- if (ctx.skip_var1 == NULL) {
- tcg_gen_brcondi_tl(ctx.skip_cond, ctx.skip_var0, 0, skip_label);
+ if (ctx->skip_var1 == NULL) {
+ tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0,
+ 0, skip_label);
} else {
- tcg_gen_brcond_tl(ctx.skip_cond, ctx.skip_var0,
- ctx.skip_var1, skip_label);
- ctx.skip_var1 = NULL;
+ tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0,
+ ctx->skip_var1, skip_label);
+ ctx->skip_var1 = NULL;
}
- if (ctx.free_skip_var0) {
- tcg_temp_free(ctx.skip_var0);
- ctx.free_skip_var0 = false;
+ if (ctx->free_skip_var0) {
+ tcg_temp_free(ctx->skip_var0);
+ ctx->free_skip_var0 = false;
}
- ctx.skip_cond = TCG_COND_NEVER;
- ctx.skip_var0 = NULL;
+ ctx->skip_cond = TCG_COND_NEVER;
+ ctx->skip_var0 = NULL;
}
- translate(&ctx);
+ translate(ctx);
if (skip_label) {
- canonicalize_skip(&ctx);
+ canonicalize_skip(ctx);
gen_set_label(skip_label);
- if (ctx.base.is_jmp == DISAS_NORETURN) {
- ctx.base.is_jmp = DISAS_CHAIN;
+ if (ctx->base.is_jmp == DISAS_NORETURN) {
+ ctx->base.is_jmp = DISAS_CHAIN;
}
}
- } while (ctx.base.is_jmp == DISAS_NEXT
+ } while (ctx->base.is_jmp == DISAS_NEXT
&& num_insns < max_insns
- && (ctx.npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4
+ && (ctx->npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4
&& !tcg_op_buf_full());
if (tb->cflags & CF_LAST_IO) {
gen_io_end();
}
- bool nonconst_skip = canonicalize_skip(&ctx);
+ bool nonconst_skip = canonicalize_skip(ctx);
- switch (ctx.base.is_jmp) {
+ switch (ctx->base.is_jmp) {
case DISAS_NORETURN:
assert(!nonconst_skip);
break;
@@ -3013,19 +3015,19 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
case DISAS_CHAIN:
if (!nonconst_skip) {
/* Note gen_goto_tb checks singlestep. */
- gen_goto_tb(&ctx, 1, ctx.npc);
+ gen_goto_tb(ctx, 1, ctx->npc);
break;
}
- tcg_gen_movi_tl(cpu_pc, ctx.npc);
+ tcg_gen_movi_tl(cpu_pc, ctx->npc);
/* fall through */
case DISAS_LOOKUP:
- if (!ctx.base.singlestep_enabled) {
+ if (!ctx->base.singlestep_enabled) {
tcg_gen_lookup_and_goto_ptr();
break;
}
/* fall through */
case DISAS_EXIT:
- if (ctx.base.singlestep_enabled) {
+ if (ctx->base.singlestep_enabled) {
gen_helper_debug(cpu_env);
} else {
tcg_gen_exit_tb(NULL, 0);
@@ -3038,7 +3040,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
done_generating:
gen_tb_end(tb, num_insns);
- tb->size = (ctx.npc - pc_start) * 2;
+ tb->size = (ctx->npc - pc_start) * 2;
tb->icount = num_insns;
#ifdef DEBUG_DISAS
--
2.25.1
next prev parent reply other threads:[~2021-06-29 19:31 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-29 18:53 [PULL 00/63] tcg patch queue Richard Henderson
2021-06-29 18:53 ` [PULL 01/63] target/nios2: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
2021-06-29 18:53 ` [PULL 02/63] target/nios2: Use global cpu_env Richard Henderson
2021-06-29 18:53 ` [PULL 03/63] target/nios2: Use global cpu_R Richard Henderson
2021-06-29 18:53 ` [PULL 04/63] target/nios2: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:53 ` [PULL 05/63] target/nios2: Convert to TranslatorOps Richard Henderson
2021-06-29 18:53 ` [PULL 06/63] target/nios2: Remove assignment to env in handle_instruction Richard Henderson
2021-06-29 18:53 ` [PULL 07/63] target/nios2: Clean up goto " Richard Henderson
2021-06-29 18:54 ` [PULL 08/63] target/nios2: Inline handle_instruction Richard Henderson
2021-06-29 18:54 ` [PULL 09/63] target/nios2: Use pc_next for pc + 4 Richard Henderson
2021-06-29 18:54 ` [PULL 10/63] target/avr: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:54 ` Richard Henderson [this message]
2021-06-29 18:54 ` [PULL 12/63] target/avr: Convert to TranslatorOps Richard Henderson
2021-06-29 18:54 ` [PULL 13/63] target/cris: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:54 ` [PULL 14/63] target/cris: Remove DISAS_SWI Richard Henderson
2021-06-29 18:54 ` [PULL 15/63] target/cris: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
2021-06-29 18:54 ` [PULL 16/63] target/cris: Mark exceptions as DISAS_NORETURN Richard Henderson
2021-06-29 18:54 ` [PULL 17/63] target/cris: Fix use_goto_tb Richard Henderson
2021-06-29 18:54 ` [PULL 18/63] target/cris: Convert to TranslatorOps Richard Henderson
2021-06-29 18:54 ` [PULL 19/63] target/cris: Mark helper_raise_exception noreturn Richard Henderson
2021-06-29 18:54 ` [PULL 20/63] target/cris: Mark static arrays const Richard Henderson
2021-06-29 18:54 ` [PULL 21/63] target/cris: Fold unhandled X_FLAG changes into cpustate_changed Richard Henderson
2021-06-29 18:54 ` [PULL 22/63] target/cris: Set cpustate_changed for rfe/rfn Richard Henderson
2021-06-29 18:54 ` [PULL 23/63] target/cris: Add DISAS_UPDATE_NEXT Richard Henderson
2021-06-29 18:54 ` [PULL 24/63] target/cris: Add DISAS_DBRANCH Richard Henderson
2021-06-29 18:54 ` [PULL 25/63] target/cris: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2021-06-29 18:54 ` [PULL 26/63] target/cris: Improve JMP_INDIRECT Richard Henderson
2021-06-29 18:54 ` [PULL 27/63] target/cris: Remove dc->flagx_known Richard Henderson
2021-06-29 18:54 ` [PULL 28/63] target/cris: Do not exit tb for X_FLAG changes Richard Henderson
2021-06-29 18:54 ` [PULL 29/63] tcg: Add tcg_gen_vec_add{sub}16_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 31/63] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 32/63] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 33/63] tcg: Implement tcg_gen_vec_add{sub}32_tl Richard Henderson
2021-06-29 18:54 ` [PULL 34/63] tcg: Use correct trap number for page faults on *BSD systems Richard Henderson
2021-06-29 18:54 ` [PULL 35/63] tcg: Add flags argument to bswap opcodes Richard Henderson
2021-06-29 18:54 ` [PULL 36/63] tcg/i386: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 37/63] tcg/aarch64: Merge tcg_out_rev{16,32,64} Richard Henderson
2021-06-29 18:54 ` [PULL 38/63] tcg/aarch64: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 39/63] tcg/arm: " Richard Henderson
2021-06-29 18:54 ` [PULL 40/63] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
2021-06-29 18:54 ` [PULL 41/63] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
2021-06-29 18:54 ` [PULL 42/63] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
2021-06-29 18:54 ` [PULL 43/63] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
2021-06-29 18:54 ` [PULL 44/63] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
2021-06-29 18:54 ` [PULL 45/63] tcg/ppc: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 46/63] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
2021-06-29 18:54 ` [PULL 47/63] tcg/s390: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 48/63] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
2021-06-29 18:54 ` [PULL 49/63] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
2021-06-29 18:54 ` [PULL 50/63] tcg/tci: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 51/63] tcg: Handle new bswap flags during optimize Richard Henderson
2021-06-29 18:54 ` [PULL 52/63] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
2021-06-29 18:54 ` [PULL 53/63] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
2021-06-29 18:54 ` [PULL 54/63] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
2021-06-29 18:54 ` [PULL 55/63] target/arm: Improve REV32 Richard Henderson
2021-06-29 18:54 ` [PULL 56/63] target/arm: Improve vector REV Richard Henderson
2021-06-29 18:54 ` [PULL 57/63] target/arm: Improve REVSH Richard Henderson
2021-06-29 18:54 ` [PULL 58/63] target/i386: Improve bswap translation Richard Henderson
2021-06-29 18:54 ` [PULL 59/63] target/sh4: Improve swap.b translation Richard Henderson
2021-06-29 18:54 ` [PULL 60/63] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
2021-06-29 18:54 ` [PULL 61/63] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Richard Henderson
2021-06-29 18:54 ` [PULL 62/63] tcg/aarch64: " Richard Henderson
2021-06-29 18:54 ` [PULL 63/63] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
2021-07-02 7:21 ` [PULL 00/63] tcg patch queue Peter Maydell
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