From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E . Iglesias" <edgar.iglesias@xilinx.com>
Subject: [PULL 24/63] target/cris: Add DISAS_DBRANCH
Date: Tue, 29 Jun 2021 11:54:16 -0700 [thread overview]
Message-ID: <20210629185455.3131172-25-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210629185455.3131172-1-richard.henderson@linaro.org>
Move delayed branch handling to tb_stop, where we can re-use other
end-of-tb code, e.g. the evaluation of flags. Honor single stepping.
Validate that we aren't losing state by overwriting is_jmp.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/translate.c | 96 ++++++++++++++++++++++++-----------------
1 file changed, 56 insertions(+), 40 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index a2124ffcd5..7035426a9c 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -61,6 +61,8 @@
#define DISAS_UPDATE DISAS_TARGET_1
/* Cpu state was modified dynamically, excluding pc -- use npc */
#define DISAS_UPDATE_NEXT DISAS_TARGET_2
+/* PC update for delayed branch, see cpustate_changed otherwise */
+#define DISAS_DBRANCH DISAS_TARGET_3
/* Used by the decoder. */
#define EXTRACT_FIELD(src, start, end) \
@@ -3230,50 +3232,22 @@ static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
dc->cpustate_changed |= dc->flags_x != (dc->base.tb->flags & X_FLAG);
/*
- * Check for delayed branches here. If we do it before
- * actually generating any host code, the simulator will just
- * loop doing nothing for on this program location.
+ * All branches are delayed branches, handled immediately below.
+ * We don't expect to see odd combinations of exit conditions.
*/
+ assert(dc->base.is_jmp == DISAS_NEXT || dc->cpustate_changed);
+
if (dc->delayed_branch && --dc->delayed_branch == 0) {
- if (dc->base.tb->flags & 7) {
- t_gen_movi_env_TN(dslot, 0);
- }
+ dc->base.is_jmp = DISAS_DBRANCH;
+ return;
+ }
- if (dc->cpustate_changed) {
- cris_store_direct_jmp(dc);
- }
-
- if (dc->clear_locked_irq) {
- dc->clear_locked_irq = 0;
- t_gen_movi_env_TN(locked_irq, 0);
- }
-
- if (dc->jmp == JMP_DIRECT_CC) {
- TCGLabel *l1 = gen_new_label();
- cris_evaluate_flags(dc);
-
- /* Conditional jmp. */
- tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
- gen_goto_tb(dc, 1, dc->jmp_pc);
- gen_set_label(l1);
- gen_goto_tb(dc, 0, dc->pc);
- dc->base.is_jmp = DISAS_NORETURN;
- dc->jmp = JMP_NOJMP;
- } else if (dc->jmp == JMP_DIRECT) {
- cris_evaluate_flags(dc);
- gen_goto_tb(dc, 0, dc->jmp_pc);
- dc->base.is_jmp = DISAS_NORETURN;
- dc->jmp = JMP_NOJMP;
- } else {
- TCGv c = tcg_const_tl(dc->pc);
- t_gen_cc_jmp(env_btarget, c);
- tcg_temp_free(c);
- dc->base.is_jmp = DISAS_JUMP;
- }
+ if (dc->base.is_jmp != DISAS_NEXT) {
+ return;
}
/* Force an update if the per-tb cpu state has changed. */
- if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) {
+ if (dc->cpustate_changed) {
dc->base.is_jmp = DISAS_UPDATE_NEXT;
return;
}
@@ -3283,8 +3257,7 @@ static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
* If we can detect the length of the next insn easily, we should.
* In the meantime, simply stop when we do cross.
*/
- if (dc->base.is_jmp == DISAS_NEXT
- && ((dc->pc ^ dc->base.pc_first) & TARGET_PAGE_MASK) != 0) {
+ if ((dc->pc ^ dc->base.pc_first) & TARGET_PAGE_MASK) {
dc->base.is_jmp = DISAS_TOO_MANY;
}
}
@@ -3314,6 +3287,49 @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
cris_evaluate_flags(dc);
+ /* Evaluate delayed branch destination and fold to another is_jmp case. */
+ if (is_jmp == DISAS_DBRANCH) {
+ if (dc->base.tb->flags & 7) {
+ t_gen_movi_env_TN(dslot, 0);
+ }
+
+ switch (dc->jmp) {
+ case JMP_DIRECT:
+ npc = dc->jmp_pc;
+ is_jmp = dc->cpustate_changed ? DISAS_UPDATE_NEXT : DISAS_TOO_MANY;
+ break;
+
+ case JMP_DIRECT_CC:
+ /*
+ * Use a conditional branch if either taken or not-taken path
+ * can use goto_tb. If neither can, then treat it as indirect.
+ */
+ if (likely(!dc->base.singlestep_enabled)
+ && likely(!dc->cpustate_changed)
+ && (use_goto_tb(dc, dc->jmp_pc) || use_goto_tb(dc, npc))) {
+ TCGLabel *not_taken = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, not_taken);
+ gen_goto_tb(dc, 1, dc->jmp_pc);
+ gen_set_label(not_taken);
+
+ /* not-taken case handled below. */
+ is_jmp = DISAS_TOO_MANY;
+ break;
+ }
+ tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
+ /* fall through */
+
+ case JMP_INDIRECT:
+ t_gen_cc_jmp(env_btarget, tcg_constant_tl(npc));
+ is_jmp = dc->cpustate_changed ? DISAS_UPDATE : DISAS_JUMP;
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ }
+
if (unlikely(dc->base.singlestep_enabled)) {
switch (is_jmp) {
case DISAS_TOO_MANY:
--
2.25.1
next prev parent reply other threads:[~2021-06-29 19:17 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-29 18:53 [PULL 00/63] tcg patch queue Richard Henderson
2021-06-29 18:53 ` [PULL 01/63] target/nios2: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
2021-06-29 18:53 ` [PULL 02/63] target/nios2: Use global cpu_env Richard Henderson
2021-06-29 18:53 ` [PULL 03/63] target/nios2: Use global cpu_R Richard Henderson
2021-06-29 18:53 ` [PULL 04/63] target/nios2: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:53 ` [PULL 05/63] target/nios2: Convert to TranslatorOps Richard Henderson
2021-06-29 18:53 ` [PULL 06/63] target/nios2: Remove assignment to env in handle_instruction Richard Henderson
2021-06-29 18:53 ` [PULL 07/63] target/nios2: Clean up goto " Richard Henderson
2021-06-29 18:54 ` [PULL 08/63] target/nios2: Inline handle_instruction Richard Henderson
2021-06-29 18:54 ` [PULL 09/63] target/nios2: Use pc_next for pc + 4 Richard Henderson
2021-06-29 18:54 ` [PULL 10/63] target/avr: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:54 ` [PULL 11/63] target/avr: Change ctx to DisasContext* in gen_intermediate_code Richard Henderson
2021-06-29 18:54 ` [PULL 12/63] target/avr: Convert to TranslatorOps Richard Henderson
2021-06-29 18:54 ` [PULL 13/63] target/cris: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:54 ` [PULL 14/63] target/cris: Remove DISAS_SWI Richard Henderson
2021-06-29 18:54 ` [PULL 15/63] target/cris: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
2021-06-29 18:54 ` [PULL 16/63] target/cris: Mark exceptions as DISAS_NORETURN Richard Henderson
2021-06-29 18:54 ` [PULL 17/63] target/cris: Fix use_goto_tb Richard Henderson
2021-06-29 18:54 ` [PULL 18/63] target/cris: Convert to TranslatorOps Richard Henderson
2021-06-29 18:54 ` [PULL 19/63] target/cris: Mark helper_raise_exception noreturn Richard Henderson
2021-06-29 18:54 ` [PULL 20/63] target/cris: Mark static arrays const Richard Henderson
2021-06-29 18:54 ` [PULL 21/63] target/cris: Fold unhandled X_FLAG changes into cpustate_changed Richard Henderson
2021-06-29 18:54 ` [PULL 22/63] target/cris: Set cpustate_changed for rfe/rfn Richard Henderson
2021-06-29 18:54 ` [PULL 23/63] target/cris: Add DISAS_UPDATE_NEXT Richard Henderson
2021-06-29 18:54 ` Richard Henderson [this message]
2021-06-29 18:54 ` [PULL 25/63] target/cris: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2021-06-29 18:54 ` [PULL 26/63] target/cris: Improve JMP_INDIRECT Richard Henderson
2021-06-29 18:54 ` [PULL 27/63] target/cris: Remove dc->flagx_known Richard Henderson
2021-06-29 18:54 ` [PULL 28/63] target/cris: Do not exit tb for X_FLAG changes Richard Henderson
2021-06-29 18:54 ` [PULL 29/63] tcg: Add tcg_gen_vec_add{sub}16_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 31/63] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 32/63] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 33/63] tcg: Implement tcg_gen_vec_add{sub}32_tl Richard Henderson
2021-06-29 18:54 ` [PULL 34/63] tcg: Use correct trap number for page faults on *BSD systems Richard Henderson
2021-06-29 18:54 ` [PULL 35/63] tcg: Add flags argument to bswap opcodes Richard Henderson
2021-06-29 18:54 ` [PULL 36/63] tcg/i386: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 37/63] tcg/aarch64: Merge tcg_out_rev{16,32,64} Richard Henderson
2021-06-29 18:54 ` [PULL 38/63] tcg/aarch64: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 39/63] tcg/arm: " Richard Henderson
2021-06-29 18:54 ` [PULL 40/63] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
2021-06-29 18:54 ` [PULL 41/63] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
2021-06-29 18:54 ` [PULL 42/63] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
2021-06-29 18:54 ` [PULL 43/63] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
2021-06-29 18:54 ` [PULL 44/63] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
2021-06-29 18:54 ` [PULL 45/63] tcg/ppc: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 46/63] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
2021-06-29 18:54 ` [PULL 47/63] tcg/s390: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 48/63] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
2021-06-29 18:54 ` [PULL 49/63] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
2021-06-29 18:54 ` [PULL 50/63] tcg/tci: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 51/63] tcg: Handle new bswap flags during optimize Richard Henderson
2021-06-29 18:54 ` [PULL 52/63] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
2021-06-29 18:54 ` [PULL 53/63] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
2021-06-29 18:54 ` [PULL 54/63] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
2021-06-29 18:54 ` [PULL 55/63] target/arm: Improve REV32 Richard Henderson
2021-06-29 18:54 ` [PULL 56/63] target/arm: Improve vector REV Richard Henderson
2021-06-29 18:54 ` [PULL 57/63] target/arm: Improve REVSH Richard Henderson
2021-06-29 18:54 ` [PULL 58/63] target/i386: Improve bswap translation Richard Henderson
2021-06-29 18:54 ` [PULL 59/63] target/sh4: Improve swap.b translation Richard Henderson
2021-06-29 18:54 ` [PULL 60/63] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
2021-06-29 18:54 ` [PULL 61/63] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Richard Henderson
2021-06-29 18:54 ` [PULL 62/63] tcg/aarch64: " Richard Henderson
2021-06-29 18:54 ` [PULL 63/63] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
2021-07-02 7:21 ` [PULL 00/63] tcg patch queue Peter Maydell
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