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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Juergen Lock <nox@FreeBSD.org>, Mark Johnston <markj@FreeBSD.org>,
	Warner Losh <imp@bsdimp.com>
Subject: [PULL 34/63] tcg: Use correct trap number for page faults on *BSD systems
Date: Tue, 29 Jun 2021 11:54:26 -0700	[thread overview]
Message-ID: <20210629185455.3131172-35-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210629185455.3131172-1-richard.henderson@linaro.org>

From: Warner Losh <imp@bsdimp.com>

The trap number for a page fault on BSD systems is T_PAGEFLT
not 0xe -- 0xe is used by Linux and represents the intel hardware
trap vector. The BSD kernels, however, translate this to T_PAGEFLT
in their Xpage, Xtrap0e, Xtrap14, etc fault handlers. This is true
for i386 and x86_64, though the name of the trap hanlder can very
on the flavor of BSD. As far as I can tell, Linux doesn't provide
a define for this value. Invent a new one (PAGE_FAULT_TRAP) and
use it instead to avoid uglier ifdefs.

Signed-off-by: Mark Johnston <markj@FreeBSD.org>
Signed-off-by: Juergen Lock <nox@FreeBSD.org>
[ Rework to avoid ifdefs and expand it to i386 ]
Signed-off-by: Warner Losh <imp@bsdimp.com>
Message-Id: <20210625045707.84534-3-imp@bsdimp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/user-exec.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index e67b1617b5..ba09fd0413 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -254,28 +254,35 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
 
 #if defined(__NetBSD__)
 #include <ucontext.h>
+#include <machine/trap.h>
 
 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 #define MASK_sig(context)    ((context)->uc_sigmask)
+#define PAGE_FAULT_TRAP      T_PAGEFLT
 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 #include <ucontext.h>
+#include <machine/trap.h>
 
 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 #define MASK_sig(context)    ((context)->uc_sigmask)
+#define PAGE_FAULT_TRAP      T_PAGEFLT
 #elif defined(__OpenBSD__)
+#include <machine/trap.h>
 #define EIP_sig(context)     ((context)->sc_eip)
 #define TRAP_sig(context)    ((context)->sc_trapno)
 #define ERROR_sig(context)   ((context)->sc_err)
 #define MASK_sig(context)    ((context)->sc_mask)
+#define PAGE_FAULT_TRAP      T_PAGEFLT
 #else
 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 #define MASK_sig(context)    ((context)->uc_sigmask)
+#define PAGE_FAULT_TRAP      0xe
 #endif
 
 int cpu_signal_handler(int host_signum, void *pinfo,
@@ -301,34 +308,42 @@ int cpu_signal_handler(int host_signum, void *pinfo,
     pc = EIP_sig(uc);
     trapno = TRAP_sig(uc);
     return handle_cpu_signal(pc, info,
-                             trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
+                             trapno == PAGE_FAULT_TRAP ?
+                             (ERROR_sig(uc) >> 1) & 1 : 0,
                              &MASK_sig(uc));
 }
 
 #elif defined(__x86_64__)
 
 #ifdef __NetBSD__
+#include <machine/trap.h>
 #define PC_sig(context)       _UC_MACHINE_PC(context)
 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 #define MASK_sig(context)     ((context)->uc_sigmask)
+#define PAGE_FAULT_TRAP       T_PAGEFLT
 #elif defined(__OpenBSD__)
+#include <machine/trap.h>
 #define PC_sig(context)       ((context)->sc_rip)
 #define TRAP_sig(context)     ((context)->sc_trapno)
 #define ERROR_sig(context)    ((context)->sc_err)
 #define MASK_sig(context)     ((context)->sc_mask)
+#define PAGE_FAULT_TRAP       T_PAGEFLT
 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 #include <ucontext.h>
+#include <machine/trap.h>
 
 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 #define MASK_sig(context)     ((context)->uc_sigmask)
+#define PAGE_FAULT_TRAP       T_PAGEFLT
 #else
 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 #define MASK_sig(context)     ((context)->uc_sigmask)
+#define PAGE_FAULT_TRAP       0xe
 #endif
 
 int cpu_signal_handler(int host_signum, void *pinfo,
@@ -346,7 +361,8 @@ int cpu_signal_handler(int host_signum, void *pinfo,
 
     pc = PC_sig(uc);
     return handle_cpu_signal(pc, info,
-                             TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
+                             TRAP_sig(uc) == PAGE_FAULT_TRAP ?
+                             (ERROR_sig(uc) >> 1) & 1 : 0,
                              &MASK_sig(uc));
 }
 
-- 
2.25.1



  parent reply	other threads:[~2021-06-29 19:49 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-29 18:53 [PULL 00/63] tcg patch queue Richard Henderson
2021-06-29 18:53 ` [PULL 01/63] target/nios2: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
2021-06-29 18:53 ` [PULL 02/63] target/nios2: Use global cpu_env Richard Henderson
2021-06-29 18:53 ` [PULL 03/63] target/nios2: Use global cpu_R Richard Henderson
2021-06-29 18:53 ` [PULL 04/63] target/nios2: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:53 ` [PULL 05/63] target/nios2: Convert to TranslatorOps Richard Henderson
2021-06-29 18:53 ` [PULL 06/63] target/nios2: Remove assignment to env in handle_instruction Richard Henderson
2021-06-29 18:53 ` [PULL 07/63] target/nios2: Clean up goto " Richard Henderson
2021-06-29 18:54 ` [PULL 08/63] target/nios2: Inline handle_instruction Richard Henderson
2021-06-29 18:54 ` [PULL 09/63] target/nios2: Use pc_next for pc + 4 Richard Henderson
2021-06-29 18:54 ` [PULL 10/63] target/avr: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:54 ` [PULL 11/63] target/avr: Change ctx to DisasContext* in gen_intermediate_code Richard Henderson
2021-06-29 18:54 ` [PULL 12/63] target/avr: Convert to TranslatorOps Richard Henderson
2021-06-29 18:54 ` [PULL 13/63] target/cris: Add DisasContextBase to DisasContext Richard Henderson
2021-06-29 18:54 ` [PULL 14/63] target/cris: Remove DISAS_SWI Richard Henderson
2021-06-29 18:54 ` [PULL 15/63] target/cris: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
2021-06-29 18:54 ` [PULL 16/63] target/cris: Mark exceptions as DISAS_NORETURN Richard Henderson
2021-06-29 18:54 ` [PULL 17/63] target/cris: Fix use_goto_tb Richard Henderson
2021-06-29 18:54 ` [PULL 18/63] target/cris: Convert to TranslatorOps Richard Henderson
2021-06-29 18:54 ` [PULL 19/63] target/cris: Mark helper_raise_exception noreturn Richard Henderson
2021-06-29 18:54 ` [PULL 20/63] target/cris: Mark static arrays const Richard Henderson
2021-06-29 18:54 ` [PULL 21/63] target/cris: Fold unhandled X_FLAG changes into cpustate_changed Richard Henderson
2021-06-29 18:54 ` [PULL 22/63] target/cris: Set cpustate_changed for rfe/rfn Richard Henderson
2021-06-29 18:54 ` [PULL 23/63] target/cris: Add DISAS_UPDATE_NEXT Richard Henderson
2021-06-29 18:54 ` [PULL 24/63] target/cris: Add DISAS_DBRANCH Richard Henderson
2021-06-29 18:54 ` [PULL 25/63] target/cris: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2021-06-29 18:54 ` [PULL 26/63] target/cris: Improve JMP_INDIRECT Richard Henderson
2021-06-29 18:54 ` [PULL 27/63] target/cris: Remove dc->flagx_known Richard Henderson
2021-06-29 18:54 ` [PULL 28/63] target/cris: Do not exit tb for X_FLAG changes Richard Henderson
2021-06-29 18:54 ` [PULL 29/63] tcg: Add tcg_gen_vec_add{sub}16_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 31/63] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 32/63] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32 Richard Henderson
2021-06-29 18:54 ` [PULL 33/63] tcg: Implement tcg_gen_vec_add{sub}32_tl Richard Henderson
2021-06-29 18:54 ` Richard Henderson [this message]
2021-06-29 18:54 ` [PULL 35/63] tcg: Add flags argument to bswap opcodes Richard Henderson
2021-06-29 18:54 ` [PULL 36/63] tcg/i386: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 37/63] tcg/aarch64: Merge tcg_out_rev{16,32,64} Richard Henderson
2021-06-29 18:54 ` [PULL 38/63] tcg/aarch64: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 39/63] tcg/arm: " Richard Henderson
2021-06-29 18:54 ` [PULL 40/63] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
2021-06-29 18:54 ` [PULL 41/63] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
2021-06-29 18:54 ` [PULL 42/63] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
2021-06-29 18:54 ` [PULL 43/63] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
2021-06-29 18:54 ` [PULL 44/63] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
2021-06-29 18:54 ` [PULL 45/63] tcg/ppc: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 46/63] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
2021-06-29 18:54 ` [PULL 47/63] tcg/s390: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 48/63] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
2021-06-29 18:54 ` [PULL 49/63] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
2021-06-29 18:54 ` [PULL 50/63] tcg/tci: Support bswap flags Richard Henderson
2021-06-29 18:54 ` [PULL 51/63] tcg: Handle new bswap flags during optimize Richard Henderson
2021-06-29 18:54 ` [PULL 52/63] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
2021-06-29 18:54 ` [PULL 53/63] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
2021-06-29 18:54 ` [PULL 54/63] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
2021-06-29 18:54 ` [PULL 55/63] target/arm: Improve REV32 Richard Henderson
2021-06-29 18:54 ` [PULL 56/63] target/arm: Improve vector REV Richard Henderson
2021-06-29 18:54 ` [PULL 57/63] target/arm: Improve REVSH Richard Henderson
2021-06-29 18:54 ` [PULL 58/63] target/i386: Improve bswap translation Richard Henderson
2021-06-29 18:54 ` [PULL 59/63] target/sh4: Improve swap.b translation Richard Henderson
2021-06-29 18:54 ` [PULL 60/63] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
2021-06-29 18:54 ` [PULL 61/63] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Richard Henderson
2021-06-29 18:54 ` [PULL 62/63] tcg/aarch64: " Richard Henderson
2021-06-29 18:54 ` [PULL 63/63] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
2021-07-02  7:21 ` [PULL 00/63] tcg patch queue Peter Maydell

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