From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 16/24] target/arm: Implement MVE VSRI, VSLI
Date: Fri, 2 Jul 2021 13:59:46 +0100 [thread overview]
Message-ID: <20210702125954.13247-17-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210702125954.13247-1-peter.maydell@linaro.org>
Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 9 ++++++++
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-mve.c | 3 +++
4 files changed, 62 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 8af0e7fd8cf..e452d2ef7a0 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -396,3 +396,11 @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 6e6032b25a7..c3b5366617a 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -371,3 +371,12 @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+
+# Shift-and-insert
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
+
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 8798e77cba8..24336d1d28a 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -1251,6 +1251,48 @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+/* Shift-and-insert; we always work with 64 bits at a time */
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
+ void *vm, uint32_t shift) \
+ { \
+ uint64_t *d = vd, *m = vm; \
+ uint16_t mask; \
+ uint64_t shiftmask; \
+ unsigned e; \
+ if (shift == 0 || shift == ESIZE * 8) { \
+ /* \
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
+ * The generic logic would give the right answer for 0 but \
+ * fails for <dt>. \
+ */ \
+ goto done; \
+ } \
+ assert(shift < ESIZE * 8); \
+ mask = mve_element_mask(env); \
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
+ (d[H8(e)] & ~shiftmask); \
+ mergemask(&d[H8(e)], r, mask); \
+ } \
+done: \
+ mve_advance_vpt(env); \
+ }
+
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
+
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
+
/*
* Long shifts taking half-sized inputs from top or bottom of the input
* vector and producing a double-width result. ESIZE, TYPE are for
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 044462c3752..b031f84966e 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -894,6 +894,9 @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+DO_2SHIFT(VSRI, vsri, false)
+DO_2SHIFT(VSLI, vsli, false)
+
#define DO_VSHLL(INSN, FN) \
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
{ \
--
2.20.1
next prev parent reply other threads:[~2021-07-02 13:07 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-02 12:59 [PULL 00/24] target-arm queue Peter Maydell
2021-07-02 12:59 ` [PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference Peter Maydell
2021-07-02 12:59 ` [PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference Peter Maydell
2021-07-02 12:59 ` [PULL 03/24] hw/arm: Add basic power management to raspi Peter Maydell
2021-07-02 12:59 ` [PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine Peter Maydell
2021-07-02 12:59 ` [PULL 05/24] target/arm: Check NaN mode before silencing NaN Peter Maydell
2021-07-02 12:59 ` [PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot Peter Maydell
2021-07-02 12:59 ` [PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation Peter Maydell
2021-07-02 12:59 ` [PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH Peter Maydell
2021-07-02 12:59 ` [PULL 09/24] target/arm: Make asimd_imm_const() public Peter Maydell
2021-07-02 12:59 ` [PULL 10/24] target/arm: Use asimd_imm_const for A64 decode Peter Maydell
2021-07-02 12:59 ` [PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate() Peter Maydell
2021-07-02 12:59 ` [PULL 12/24] target/arm: Implement MVE logical immediate insns Peter Maydell
2021-07-02 12:59 ` [PULL 13/24] target/arm: Implement MVE vector shift left by " Peter Maydell
2021-07-02 12:59 ` [PULL 14/24] target/arm: Implement MVE vector shift right " Peter Maydell
2021-07-02 12:59 ` [PULL 15/24] target/arm: Implement MVE VSHLL Peter Maydell
2021-07-02 12:59 ` Peter Maydell [this message]
2021-07-02 12:59 ` [PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN Peter Maydell
2021-07-02 12:59 ` [PULL 18/24] target/arm: Implement MVE saturating narrowing shifts Peter Maydell
2021-07-02 12:59 ` [PULL 19/24] target/arm: Implement MVE VSHLC Peter Maydell
2021-07-02 12:59 ` [PULL 20/24] target/arm: Implement MVE VADDLV Peter Maydell
2021-07-02 12:59 ` [PULL 21/24] target/arm: Implement MVE long shifts by immediate Peter Maydell
2021-07-02 12:59 ` [PULL 22/24] target/arm: Implement MVE long shifts by register Peter Maydell
2021-07-02 12:59 ` [PULL 23/24] target/arm: Implement MVE shifts by immediate Peter Maydell
2021-07-02 12:59 ` [PULL 24/24] target/arm: Implement MVE shifts by register Peter Maydell
2021-07-04 13:03 ` [PULL 00/24] target-arm queue Peter Maydell
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