From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org
Subject: [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store
Date: Thu, 8 Jul 2021 21:25:58 -0700 [thread overview]
Message-ID: <20210709042608.883256-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210709042608.883256-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 45 +++++++++++++++----------
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index a603925637..a422dc9ef4 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -138,15 +138,21 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
+ TCGv dest = gpr_dst(ctx, a->rd);
+ TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv temp = NULL;
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(a->rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
return true;
}
@@ -177,19 +183,24 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
- gen_get_gpr(dat, a->rs2);
+ TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv data = gpr_src(ctx, a->rs2);
+ TCGv temp = NULL;
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
return true;
}
-
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
return gen_store(ctx, a, MO_SB);
--
2.25.1
next prev parent reply other threads:[~2021-07-09 4:33 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 4:25 [PATCH 00/17] target/riscv: Use tcg_constant_* Richard Henderson
2021-07-09 4:25 ` [PATCH 01/17] " Richard Henderson
2021-07-09 5:41 ` Alistair Francis
2021-07-09 16:20 ` Philippe Mathieu-Daudé
2021-07-09 4:25 ` [PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst Richard Henderson
2021-07-09 5:45 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations Richard Henderson
2021-07-13 4:10 ` [PATCH 03/17] target/riscv: Use gpr_{src, dst} " Alistair Francis
2021-07-09 4:25 ` [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations Richard Henderson
2021-07-13 4:11 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi Richard Henderson
2021-07-13 4:12 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 06/17] target/riscv: Use gpr_src in branches Richard Henderson
2021-07-13 4:14 ` Alistair Francis
2021-07-09 4:25 ` Richard Henderson [this message]
2021-07-13 4:18 ` [PATCH 07/17] target/riscv: Use gpr_{src, dst} for integer load/store Alistair Francis
2021-07-09 4:25 ` [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations Richard Henderson
2021-07-15 4:49 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 09/17] target/riscv: Reorg csr instructions Richard Henderson
2021-07-23 5:00 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA Richard Henderson
2021-07-15 4:50 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB Richard Henderson
2021-07-15 4:52 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF Richard Henderson
2021-07-15 4:58 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD Richard Henderson
2021-07-15 5:00 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-07-23 5:02 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-07-15 5:02 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV Richard Henderson
2021-07-15 5:04 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 17/17] target/riscv: Remove gen_get_gpr Richard Henderson
2021-07-15 5:08 ` Alistair Francis
2021-07-15 11:21 ` [PATCH 00/17] target/riscv: Use tcg_constant_* LIU Zhiwei
2021-07-15 16:15 ` Richard Henderson
2021-07-17 3:59 ` LIU Zhiwei
2021-07-17 15:41 ` Richard Henderson
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