From: Andrew Jeffery <andrew@aj.id.au>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, clg@kaod.org,
joel@jms.id.au
Subject: [PATCH 0/2] wdt_aspeed: Fix behaviour of control register
Date: Fri, 9 Jul 2021 15:01:05 +0930 [thread overview]
Message-ID: <20210709053107.1829304-1-andrew@aj.id.au> (raw)
Hello,
I discovered a couple of bugs in the watchdog while testing a tool to poke
Aspeed BMCs over their various AHB bridges. The immediate observation was that
the model for the 2500 wasn't signalling use of the fixed 1MHz clock, which is
resolved in the first patch. The other observation was that sequential writes to
control weren't sticking if the enable bit wasn't toggled, which is fixed in the
second patch.
Please review.
Andrew
Andrew Jeffery (2):
watchdog: aspeed: Sanitize control register values
watchdog: aspeed: Fix sequential control writes
hw/watchdog/wdt_aspeed.c | 26 ++++++++++++++++++++++++--
include/hw/watchdog/wdt_aspeed.h | 1 +
2 files changed, 25 insertions(+), 2 deletions(-)
--
2.30.2
next reply other threads:[~2021-07-09 5:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 5:31 Andrew Jeffery [this message]
2021-07-09 5:31 ` [PATCH 1/2] watchdog: aspeed: Sanitize control register values Andrew Jeffery
2021-07-19 15:53 ` Cédric Le Goater
2021-07-09 5:31 ` [PATCH 2/2] watchdog: aspeed: Fix sequential control writes Andrew Jeffery
2021-07-09 7:29 ` Philippe Mathieu-Daudé
2021-07-13 2:41 ` Andrew Jeffery
2021-07-19 15:54 ` Cédric Le Goater
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