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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/17] hw/arm/virt: Make PL061 GPIO lines pulled low, not high
Date: Fri,  9 Jul 2021 17:09:58 +0100	[thread overview]
Message-ID: <20210709161003.25874-13-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org>

For the virt board we have two PL061 devices -- one for NonSecure which
is inputs only, and one for Secure which is outputs only. For the former,
we don't care whether its outputs are pulled low or high when the line is
configured as an input, because we don't connect them. For the latter,
we do care, because we wire the lines up to the gpio-pwr device, which
assumes that level 1 means "do the action" and 1 means "do nothing".
For consistency in case we add more outputs in future, configure both
PL061s to pull GPIO lines down to 0.

Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b96f060140..93ab9d21ea0 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -895,6 +895,9 @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
     MachineState *ms = MACHINE(vms);
 
     pl061_dev = qdev_new("pl061");
+    /* Pull lines down to 0 if not driven by the PL061 */
+    qdev_prop_set_uint32(pl061_dev, "pullups", 0);
+    qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
     s = SYS_BUS_DEVICE(pl061_dev);
     sysbus_realize_and_unref(s, &error_fatal);
     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
-- 
2.20.1



  parent reply	other threads:[~2021-07-09 16:31 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-09 16:09 [PULL 00/17] target-arm queue Peter Maydell
2021-07-09 16:09 ` [PULL 01/17] stm32f100: Add the stm32f100 SoC Peter Maydell
2021-07-09 16:09 ` [PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine Peter Maydell
2021-07-09 16:09 ` [PULL 03/17] docs/system: arm: Add stm32 boards description Peter Maydell
2021-07-09 16:09 ` [PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase Peter Maydell
2021-07-09 16:09 ` [PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write Peter Maydell
2021-07-09 16:09 ` [PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints Peter Maydell
2021-07-09 16:09 ` [PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic Peter Maydell
2021-07-09 16:09 ` [PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write Peter Maydell
2021-07-09 16:09 ` [PULL 09/17] hw/gpio/pl061: Document the interface of this device Peter Maydell
2021-07-09 16:09 ` [PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers Peter Maydell
2021-07-09 16:09 ` [PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable Peter Maydell
2021-07-09 16:09 ` Peter Maydell [this message]
2021-07-09 16:09 ` [PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset Peter Maydell
2021-07-09 16:10 ` [PULL 14/17] hw/gpio/pl061: Document a shortcoming in our implementation Peter Maydell
2021-07-09 16:10 ` [PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect Peter Maydell
2021-07-09 16:10 ` [PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint Peter Maydell
2021-07-09 16:10 ` [PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message Peter Maydell
2021-07-11 13:31 ` [PULL 00/17] target-arm queue Peter Maydell

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