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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Fredrik Noring" <noring@nocrew.org>,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"David Gibson" <david@gibson.dropbear.id.au>
Subject: [PULL 02/19] hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition
Date: Sun, 11 Jul 2021 22:59:59 +0200	[thread overview]
Message-ID: <20210711210016.2710100-3-f4bug@amsat.org> (raw)
In-Reply-To: <20210711210016.2710100-1-f4bug@amsat.org>

Rather than using the magic 0x80000000 number for the PCI I/O BAR
physical address on the main system bus, use a definition.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210417103028.601124-6-f4bug@amsat.org>
---
 hw/pci-host/raven.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index 9fef74fc56c..3be27f0a14d 100644
--- a/hw/pci-host/raven.c
+++ b/hw/pci-host/raven.c
@@ -81,6 +81,8 @@ struct PRePPCIState {
 
 #define BIOS_SIZE (1 * MiB)
 
+#define PCI_IO_BASE_ADDR    0x80000000  /* Physical address on main bus */
+
 static inline uint32_t raven_pci_io_config(hwaddr addr)
 {
     int i;
@@ -158,7 +160,7 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr,
     uint8_t buf[4];
 
     addr = raven_io_address(s, addr);
-    address_space_read(&s->pci_io_as, addr + 0x80000000,
+    address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
                        MEMTXATTRS_UNSPECIFIED, buf, size);
 
     if (size == 1) {
@@ -190,7 +192,7 @@ static void raven_io_write(void *opaque, hwaddr addr,
         g_assert_not_reached();
     }
 
-    address_space_write(&s->pci_io_as, addr + 0x80000000,
+    address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
                         MEMTXATTRS_UNSPECIFIED, buf, size);
 }
 
@@ -293,8 +295,9 @@ static void raven_pcihost_initfn(Object *obj)
     address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
 
     /* CPU address space */
-    memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
-    memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
+    memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
+                                &s->pci_io);
+    memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
                                         &s->pci_io_non_contiguous, 1);
     memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
     pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
-- 
2.31.1



  parent reply	other threads:[~2021-07-11 21:04 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-11 20:59 [PULL 00/19] MIPS patches for 2021-07-11 Philippe Mathieu-Daudé
2021-07-11 20:59 ` [PULL 01/19] hw/pci-host: Rename Raven ASIC PCI bridge as raven.c Philippe Mathieu-Daudé
2021-07-11 20:59 ` Philippe Mathieu-Daudé [this message]
2021-07-11 21:00 ` [PULL 03/19] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 04/19] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 05/19] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 06/19] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 07/19] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 08/19] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 09/19] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 10/19] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 11/19] target/mips/tx79: Introduce LQ opcode (Load Quadword) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 12/19] target/mips/tx79: Introduce SQ opcode (Store Quadword) Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 13/19] target/mips: Rewrite UHI errno_mips() using switch statement Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 14/19] dp8393x: fix CAM descriptor entry index Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 15/19] dp8393x: Replace address_space_rw(is_write=1) by address_space_write() Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 16/19] dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 17/19] dp8393x: Store CAM registers as 16-bit Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 18/19] dp8393x: Rewrite dp8393x_get() / dp8393x_put() Philippe Mathieu-Daudé
2021-07-11 21:00 ` [PULL 19/19] dp8393x: don't force 32-bit register access Philippe Mathieu-Daudé
2021-07-11 21:19 ` [PULL 00/19] MIPS patches for 2021-07-11 Philippe Mathieu-Daudé

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