From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: Jose Martins <josemartins90@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg
Date: Mon, 12 Jul 2021 15:53:42 -0700 [thread overview]
Message-ID: <20210712225348.213819-6-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210712225348.213819-1-alistair.francis@wdc.com>
From: Jose Martins <josemartins90@gmail.com>
The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.
Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210522155902.374439-1-josemartins90@gmail.com
[ Changes by AF:
- Improve indentation
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 62b968326c..b904d2bcb0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -411,6 +411,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
+static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
static const target_ulong delegable_excps =
@@ -433,6 +434,14 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
+static const target_ulong vs_delegable_excps = delegable_excps &
+ ~((1ULL << (RISCV_EXCP_S_ECALL)) |
+ (1ULL << (RISCV_EXCP_VS_ECALL)) |
+ (1ULL << (RISCV_EXCP_M_ECALL)) |
+ (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
+ (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
+ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
+ (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR;
@@ -1039,7 +1048,7 @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
target_ulong val)
{
- env->hedeleg = val;
+ env->hedeleg = val & vs_delegable_excps;
return RISCV_EXCP_NONE;
}
@@ -1053,7 +1062,7 @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno,
static RISCVException write_hideleg(CPURISCVState *env, int csrno,
target_ulong val)
{
- env->hideleg = val;
+ env->hideleg = val & vs_delegable_ints;
return RISCV_EXCP_NONE;
}
--
2.31.1
next prev parent reply other threads:[~2021-07-12 23:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-12 22:53 [PULL 00/11] riscv-to-apply queue Alistair Francis
2021-07-12 22:53 ` [PULL 01/11] target/riscv: pmp: Fix some typos Alistair Francis
2021-07-12 22:53 ` [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines Alistair Francis
2021-07-12 22:53 ` [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc Alistair Francis
2021-07-12 22:53 ` [PULL 04/11] docs/system: riscv: Add documentation for virt machine Alistair Francis
2021-07-12 22:53 ` Alistair Francis [this message]
2021-07-12 22:53 ` [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot Alistair Francis
2021-07-12 22:53 ` [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency Alistair Francis
2021-07-12 22:53 ` [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned Alistair Francis
2021-07-12 22:53 ` [PULL 09/11] char: ibex_uart: Update the register layout Alistair Francis
2021-07-12 22:53 ` [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-12 22:53 ` [PULL 11/11] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-13 18:00 ` [PULL 00/11] riscv-to-apply queue Peter Maydell
2021-07-15 6:56 ` Alistair Francis
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