From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
Date: Mon, 12 Jul 2021 15:53:43 -0700 [thread overview]
Message-ID: <20210712225348.213819-7-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210712225348.213819-1-alistair.francis@wdc.com>
From: Bin Meng <bin.meng@windriver.com>
This adds a new section in the documentation to demonstrate how to
use the new direct kernel boot feature for Microchip Icicle Kit,
other than the HSS bootflow, using an upstream U-Boot v2021.07 image
as an example.
It also updates the truth table to have a new '-dtb' column which is
required by direct kernel boot.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++++++++++++---
1 file changed, 47 insertions(+), 7 deletions(-)
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
index 54ced661e3..817d2aec9c 100644
--- a/docs/system/riscv/microchip-icicle-kit.rst
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -47,13 +47,13 @@ The user provided DTB should have the following requirements:
QEMU follows below truth table to select which payload to execute:
-===== ========== =======
--bios -kernel payload
-===== ========== =======
- N N HSS
- Y don't care HSS
- N Y kernel
-===== ========== =======
+===== ========== ========== =======
+-bios -kernel -dtb payload
+===== ========== ========== =======
+ N N don't care HSS
+ Y don't care don't care HSS
+ N Y Y kernel
+===== ========== ========== =======
The memory is set to 1537 MiB by default which is the minimum required high
memory size by HSS. A sanity check on ram size is performed in the machine
@@ -106,4 +106,44 @@ HSS output is on the first serial port (stdio) and U-Boot outputs on the
second serial port. U-Boot will automatically load the Linux kernel from
the SD card image.
+Direct Kernel Boot
+------------------
+
+Sometimes we just want to test booting a new kernel, and transforming the
+kernel image to the format required by the HSS bootflow is tedious. We can
+use '-kernel' for direct kernel booting just like other RISC-V machines do.
+
+In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is
+used to boot an S-mode payload like U-Boot or OS kernel directly.
+
+For example, the following commands show building a U-Boot image from U-Boot
+mainline v2021.07 for the Microchip Icicle Kit board:
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=riscv64-linux-
+ $ make microchip_mpfs_icicle_defconfig
+
+Then we can boot the machine by:
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \
+ -sd path/to/sdcard.img \
+ -nic user,model=cadence_gem \
+ -nic tap,ifname=tap,model=cadence_gem,script=no \
+ -display none -serial stdio \
+ -kernel path/to/u-boot/build/dir/u-boot.bin \
+ -dtb path/to/u-boot/build/dir/u-boot.dtb
+
+CAVEATS:
+
+* Check the "stdout-path" property in the /chosen node in the DTB to determine
+ which serial port is used for the serial console, e.g.: if the console is set
+ to the second serial port, change to use "-serial null -serial stdio".
+* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF image
+ ``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB hence
+ ``u-boot.bin`` has to be used which does contain one. To use the ELF image,
+ we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.
+
.. _HSS: https://github.com/polarfire-soc/hart-software-services
--
2.31.1
next prev parent reply other threads:[~2021-07-12 23:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-12 22:53 [PULL 00/11] riscv-to-apply queue Alistair Francis
2021-07-12 22:53 ` [PULL 01/11] target/riscv: pmp: Fix some typos Alistair Francis
2021-07-12 22:53 ` [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines Alistair Francis
2021-07-12 22:53 ` [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc Alistair Francis
2021-07-12 22:53 ` [PULL 04/11] docs/system: riscv: Add documentation for virt machine Alistair Francis
2021-07-12 22:53 ` [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg Alistair Francis
2021-07-12 22:53 ` Alistair Francis [this message]
2021-07-12 22:53 ` [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency Alistair Francis
2021-07-12 22:53 ` [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned Alistair Francis
2021-07-12 22:53 ` [PULL 09/11] char: ibex_uart: Update the register layout Alistair Francis
2021-07-12 22:53 ` [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-12 22:53 ` [PULL 11/11] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-13 18:00 ` [PULL 00/11] riscv-to-apply queue Peter Maydell
2021-07-15 6:56 ` Alistair Francis
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