From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency
Date: Mon, 12 Jul 2021 15:53:44 -0700 [thread overview]
Message-ID: <20210712225348.213819-8-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210712225348.213819-1-alistair.francis@wdc.com>
From: Bin Meng <bin.meng@windriver.com>
At present the CLINT timebase frequency is set to 10MHz on sifive_u,
but on the real hardware the timebase frequency is 1Mhz.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 273c86418c..e75ca38783 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -62,6 +62,9 @@
#include <libfdt.h>
+/* CLINT timebase frequency */
+#define CLINT_TIMEBASE_FREQ 1000000
+
static const MemMapEntry sifive_u_memmap[] = {
[SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
@@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/cpus");
qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
- SIFIVE_CLINT_TIMEBASE_FREQ);
+ CLINT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
@@ -847,7 +850,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
--
2.31.1
next prev parent reply other threads:[~2021-07-12 22:55 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-12 22:53 [PULL 00/11] riscv-to-apply queue Alistair Francis
2021-07-12 22:53 ` [PULL 01/11] target/riscv: pmp: Fix some typos Alistair Francis
2021-07-12 22:53 ` [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines Alistair Francis
2021-07-12 22:53 ` [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc Alistair Francis
2021-07-12 22:53 ` [PULL 04/11] docs/system: riscv: Add documentation for virt machine Alistair Francis
2021-07-12 22:53 ` [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg Alistair Francis
2021-07-12 22:53 ` [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot Alistair Francis
2021-07-12 22:53 ` Alistair Francis [this message]
2021-07-12 22:53 ` [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned Alistair Francis
2021-07-12 22:53 ` [PULL 09/11] char: ibex_uart: Update the register layout Alistair Francis
2021-07-12 22:53 ` [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-12 22:53 ` [PULL 11/11] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-13 18:00 ` [PULL 00/11] riscv-to-apply queue Peter Maydell
2021-07-15 6:56 ` Alistair Francis
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