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* [PULL 00/11] riscv-to-apply queue
@ 2021-07-12 22:53 Alistair Francis
  2021-07-12 22:53 ` [PULL 01/11] target/riscv: pmp: Fix some typos Alistair Francis
                   ` (11 more replies)
  0 siblings, 12 replies; 14+ messages in thread
From: Alistair Francis @ 2021-07-12 22:53 UTC (permalink / raw)
  To: peter.maydell, qemu-devel; +Cc: Alistair Francis

The following changes since commit 57e28d34c0cb04abf7683ac6a12c87ede447c320:

  Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210708' into staging (2021-07-12 19:15:11 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210712

for you to fetch changes up to d6b87906f09f72a837dc68c33bfc3d913ef74b7d:

  hw/riscv: opentitan: Add the flash alias (2021-07-13 08:47:52 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 6.1 release

 - Code cleanups
 - Documentation improvements
 - Hypervisor extension improvements with hideleg and hedeleg
 - sifive_u fixes
 - OpenTitan register layout updates

----------------------------------------------------------------
Alistair Francis (3):
      char: ibex_uart: Update the register layout
      hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
      hw/riscv: opentitan: Add the flash alias

Bin Meng (7):
      target/riscv: pmp: Fix some typos
      target/riscv: csr: Remove redundant check in fp csr read/write routines
      docs/system: riscv: Fix CLINT name in the sifive_u doc
      docs/system: riscv: Add documentation for virt machine
      docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
      hw/riscv: sifive_u: Correct the CLINT timebase frequency
      hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned

Jose Martins (1):
      target/riscv: hardwire bits in hideleg and hedeleg

 docs/system/riscv/microchip-icicle-kit.rst |  54 +++++++++--
 docs/system/riscv/sifive_u.rst             |   2 +-
 docs/system/riscv/virt.rst                 | 138 +++++++++++++++++++++++++++++
 docs/system/target-riscv.rst               |   1 +
 include/hw/riscv/opentitan.h               |   3 +
 hw/char/ibex_uart.c                        |  19 ++--
 hw/riscv/opentitan.c                       |   9 ++
 hw/riscv/sifive_u.c                        |  12 ++-
 target/riscv/csr.c                         |  37 +++-----
 target/riscv/pmp.c                         |  10 +--
 10 files changed, 233 insertions(+), 52 deletions(-)
 create mode 100644 docs/system/riscv/virt.rst


^ permalink raw reply	[flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-07-15  6:58 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-07-12 22:53 [PULL 00/11] riscv-to-apply queue Alistair Francis
2021-07-12 22:53 ` [PULL 01/11] target/riscv: pmp: Fix some typos Alistair Francis
2021-07-12 22:53 ` [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines Alistair Francis
2021-07-12 22:53 ` [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc Alistair Francis
2021-07-12 22:53 ` [PULL 04/11] docs/system: riscv: Add documentation for virt machine Alistair Francis
2021-07-12 22:53 ` [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg Alistair Francis
2021-07-12 22:53 ` [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot Alistair Francis
2021-07-12 22:53 ` [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency Alistair Francis
2021-07-12 22:53 ` [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned Alistair Francis
2021-07-12 22:53 ` [PULL 09/11] char: ibex_uart: Update the register layout Alistair Francis
2021-07-12 22:53 ` [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-12 22:53 ` [PULL 11/11] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-13 18:00 ` [PULL 00/11] riscv-to-apply queue Peter Maydell
2021-07-15  6:56   ` Alistair Francis

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