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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j6sm9827443wrm.97.2021.07.13.06.37.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 06:37:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 00/34] target/arm: Third slice of MVE implementation Date: Tue, 13 Jul 2021 14:36:52 +0100 Message-Id: <20210713133726.26842-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchseries provides the third slice of the MVE implementation. In this series: * fixes for minor bugs in a couple of the insns already upstream * all the remaining integer instructions * the remaining loads and stores (scatter-gather and interleaving) This is obviously for-6.2 material, so no urgency in reviewing it. But "all the integer stuff done" seemed like an obvious natural break point to send out what I've done so far. I apologize in advance for the final patch, which was tricky for me to write and is probably going to be painful to review too. This is mostly because I find the interleaving loads/stores rather confusing... thanks -- PMM Peter Maydell (34): target/arm: Note that we handle VMOVL as a special case of VSHLL target/arm: Print MVE VPR in CPU dumps target/arm: Fix MVE VSLI by 0 and VSRI by
target/arm: Fix signed VADDV target/arm: Fix mask handling for MVE narrowing operations target/arm: Fix 48-bit saturating shifts target/arm: Fix calculation of LTP mask when LR is 0 target/arm: Fix VPT advance when ECI is non-zero target/arm: Factor out mve_eci_mask() target/arm: Fix VLDRB/H/W for predicated elements target/arm: Implement MVE VMULL (polynomial) target/arm: Implement MVE incrementing/decrementing dup insns target/arm: Factor out gen_vpst() target/arm: Implement MVE integer vector comparisons target/arm: Implement MVE integer vector-vs-scalar comparisons target/arm: Implement MVE VPSEL target/arm: Implement MVE VMLAS target/arm: Implement MVE shift-by-scalar target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats target/arm: Implement MVE integer min/max across vector target/arm: Implement MVE VABAV target/arm: Implement MVE narrowing moves target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn target/arm: Implement MVE VMLADAV and VMLSLDAV target/arm: Implement MVE VMLA target/arm: Implement MVE saturating doubling multiply accumulates target/arm: Implement MVE VQABS, VQNEG target/arm: Implement MVE VMAXA, VMINA target/arm: Implement MVE VMOV to/from 2 general-purpose registers target/arm: Implement MVE VPNOT target/arm: Implement MVE VCTP target/arm: Implement MVE scatter-gather insns target/arm: Implement MVE scatter-gather immediate forms target/arm: Implement MVE interleaving loads/stores target/arm/helper-mve.h | 295 +++++++++ target/arm/translate-a32.h | 2 + target/arm/vec_internal.h | 11 + target/arm/mve.decode | 228 ++++++- target/arm/t32.decode | 1 + target/arm/cpu.c | 3 + target/arm/mve_helper.c | 1259 ++++++++++++++++++++++++++++++++++-- target/arm/translate-mve.c | 865 ++++++++++++++++++++++++- target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 33 + target/arm/vec_helper.c | 14 +- 11 files changed, 2628 insertions(+), 85 deletions(-) -- 2.20.1