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Wed, 14 Jul 2021 11:39:05 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20210714113905epsmtrp20b35d65c74884b1671ced0a95caa9eb8~RpVnXxRGd0216802168epsmtrp2A; Wed, 14 Jul 2021 11:39:05 +0000 (GMT) X-AuditID: b6c32a49-f65ff7000001da4a-8d-60eed356ab61 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id D4.FD.08394.9DCCEE06; Wed, 14 Jul 2021 20:39:05 +0900 (KST) Received: from 2030045822 (unknown [107.108.221.178]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20210714113903epsmtip192fd26c267c666e84d2ad09e7483c897~RpVlRepPh1239412394epsmtip1O; Wed, 14 Jul 2021 11:39:03 +0000 (GMT) Date: Wed, 14 Jul 2021 17:05:18 +0530 From: Gollu Appalanaidu To: Klaus Jensen Subject: Re: [PATCH v3 1/5] hw/nvme: split pmrmsc register into upper and lower Message-ID: <20210714113518.GA28548@2030045822> MIME-Version: 1.0 In-Reply-To: <20210714060125.994882-2-its@irrelevant.dk> User-Agent: Mutt/1.9.4 (2018-02-28) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGJsWRmVeSWpSXmKPExsWy7bCmum7Y5XcJBjM2aFtc2X+e0WL/wW+s Ficb97BaTDp0jdFiycVUi08NUhbzbilb7N/2j9VizpkHLBa9y36zW8x6185mcbx3B4vF60n/ WS1WHrNx4PP4ca6dzePcjvPsHptWdbJ53Lm2h83jybXNTB7v911l8+jbsooxgD0qxyYjNTEl tUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6GAlhbLEnFKgUEBi cbGSvp1NUX5pSapCRn5xia1SakFKToGhUYFecWJucWleul5yfq6VoYGBkSlQZUJORsfXiywF OxUqTkzvYWtgXCvZxcjBISFgItF/2qmLkYtDSGA3o0TT/GUsEM4nRol9h+azQzjfGCU6mrsY uxg5wTq+9H9hhEjsZZRYdWAllPOKUaKh9wYrSBWLgKpE+4+lzCA2m4CRxOy3b8C6RQRUJJ7+ 2wu2g1ngCrPEzq8fmEASwgKBEl/33GQHsXkF9CWWHTvABmELSpyc+YQFxOYUsJB4cGQlWI2o gLLEgW3HmUAGSQgc4JDYfGEuK8R9LhInTmxih7CFJV4d3wJlS0l8frcXaCg7kF0tcbgIorWD UeLY5Q1sECX2Ev+eTQM7lFkgU+LDnA9QI2Ulpp5axwQR55Po/f2ECSLOK7FjHoytJrHg1neo VTISM//chur1kFi6ZyaYLSSwk1Hi8/SCCYzys5C8NgvJOgjbSqLzQxOQzQFkS0ss/8cBYWpK rN+lv4CRdRWjZGpBcW56arFpgWFeajlyhG9iBCdoLc8djHcffNA7xMjEwXiIUYKDWUmEd6nR 2wQh3pTEyqrUovz4otKc1OJDjKbAuJrILCWanA/MEXkl8YamRmZmBpYGpsYWZoZK4rxL2Q8l CAmkJ5akZqemFqQWwfQxcXBKNTBti3/U88N8V1XUPm0DzedNtR0HfjdKL/vw22m6x6NLeVKn vc+eqfo96VfQhvuGK+8nyLfOrLpZwMWwoStH4/mDB3fWJoU4H/xw0PP8M8NWcRON9cxMn33W x0orlylydm159DZx6eUk8QuGkheCBRzjY+e1uR03CUl9svPKzVShted/SFruibq3S+Pcjo1B f9++W/BP5sNh5vl730e7an5vzpn3P37ltc87q1gfzHS0Sz+pEpL0Wu3b9c011+VcJtb7eMrP 17n0/nzKldIId5dXeuKqxu/+R0rvabfXTvIKLnSr6nNUOT9D5g/Pbf5X10P3MN9cuPXDvmvT zhbbnV6xatvl957OKQwHOOZLnrY8pcRSnJFoqMVcVJwIAO1hdJhZBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42LZdlhJTvfmmXcJBnOPK1tc2X+e0WL/wW+s Ficb97BaTDp0jdFiycVUi08NUhbzbilb7N/2j9VizpkHLBa9y36zW8x6185mcbx3B4vF60n/ WS1WHrNx4PP4ca6dzePcjvPsHptWdbJ53Lm2h83jybXNTB7v911l8+jbsooxgD2KyyYlNSez LLVI3y6BK+PehAfMBS9kK84fPMjcwPhNrIuRk0NCwETiS/8Xxi5GLg4hgd2MEhN+v2GHSMhI /Do1lRnCFpZY+e85O0TRC0aJlS9nMoIkWARUJdp/LAUrYhMwkpj99g1YXERAReLpv70sIA3M AjeYJSY+6GUCSQgLBEp83XMTbAOvgL7EsmMH2EBsIYFUie4NVxgh4oISJ2c+YQGxmQXMJOZt fgi0gAPIlpZY/o8DJMwpYCHx4MhKsDGiAsoSB7YdZ5rAKDgLSfcsJN2zELoXMDKvYpRMLSjO Tc8tNiwwzEst1ytOzC0uzUvXS87P3cQIjiwtzR2M21d90DvEyMTBeIhRgoNZSYR3qdHbBCHe lMTKqtSi/Pii0pzU4kOM0hwsSuK8F7pOxgsJpCeWpGanphakFsFkmTg4pRqYtmdfzA6+Ky94 +57c+rtmiy/daXa1PXPucPS2l1+fXj23/riWi0Ck2xVD1icOG1k43K466mR93bvkaU3E1Fkh Z+wmBP3ttrCclc7s37BGeuOe1Wl6v/7d8U8XVs+0+vRiUeRk3YjeDLHPz5+cVdHT5694ZMCS Nb2mqmUOQ0vXExUh9gudC4yucKrOX+XrvF8nwCWTrVY4+KtZjnrnd6eqqSuUczbKZFtz/amN 28V7zP9cGOu3gG+z/hw5Ecx1L/Zn27+96fsNNjkmHNW2FA2qSAlQ6n0WW3TvgQfXnoreDxrC B98d38Au/2OzF1NVnPUsg7D16h9C/gtlrA0v89mj/kiYu07wMEf+JuPu1EAlluKMREMt5qLi RAB+FxwyGwMAAA== X-CMS-MailID: 20210714113905epcas5p3d582216af16ab401f806757cad6bcc8d X-Msg-Generator: CA Content-Type: multipart/mixed; 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charset="utf-8"; format="flowed" Content-Disposition: inline On Wed, Jul 14, 2021 at 08:01:21AM +0200, Klaus Jensen wrote: >From: Klaus Jensen > >The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to >make up the 64 bit logical PMRMSC register. > >Make it so. > >Signed-off-by: Klaus Jensen >--- > include/block/nvme.h | 31 ++++++++++++++++--------------- > hw/nvme/ctrl.c | 9 +++++---- > 2 files changed, 21 insertions(+), 19 deletions(-) > >diff --git a/include/block/nvme.h b/include/block/nvme.h >index 527105fafc0b..84053b68b987 100644 >--- a/include/block/nvme.h >+++ b/include/block/nvme.h >@@ -26,7 +26,8 @@ typedef struct QEMU_PACKED NvmeBar { > uint32_t pmrsts; > uint32_t pmrebs; > uint32_t pmrswtp; >- uint64_t pmrmsc; >+ uint32_t pmrmscl; >+ uint32_t pmrmscu; > uint8_t css[484]; > } NvmeBar; > >@@ -475,25 +476,25 @@ enum NvmePmrswtpMask { > #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ > (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) > >-enum NvmePmrmscShift { >- PMRMSC_CMSE_SHIFT = 1, >- PMRMSC_CBA_SHIFT = 12, >+enum NvmePmrmsclShift { >+ PMRMSCL_CMSE_SHIFT = 1, >+ PMRMSCL_CBA_SHIFT = 12, > }; > >-enum NvmePmrmscMask { >- PMRMSC_CMSE_MASK = 0x1, >- PMRMSC_CBA_MASK = 0xfffffffffffff, >+enum NvmePmrmsclMask { >+ PMRMSCL_CMSE_MASK = 0x1, >+ PMRMSCL_CBA_MASK = 0xfffff, > }; > >-#define NVME_PMRMSC_CMSE(pmrmsc) \ >- ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) >-#define NVME_PMRMSC_CBA(pmrmsc) \ >- ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) >+#define NVME_PMRMSCL_CMSE(pmrmscl) \ >+ ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) >+#define NVME_PMRMSCL_CBA(pmrmscl) \ >+ ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) > >-#define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ >- (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) >-#define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ >- (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) >+#define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ >+ (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT) >+#define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ >+ (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) > > enum NvmeSglDescriptorType { > NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, >diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c >index 2f0524e12a36..28299c6f3764 100644 >--- a/hw/nvme/ctrl.c >+++ b/hw/nvme/ctrl.c >@@ -5916,11 +5916,12 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, > return; > } > >- n->bar.pmrmsc = (n->bar.pmrmsc & ~0xffffffff) | (data & 0xffffffff); >+ n->bar.pmrmscl = data & 0xffffffff; > n->pmr.cmse = false; > >- if (NVME_PMRMSC_CMSE(n->bar.pmrmsc)) { >- hwaddr cba = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT; >+ if (NVME_PMRMSCL_CMSE(n->bar.pmrmscl)) { >+ hwaddr cba = n->bar.pmrmscu | >+ (NVME_PMRMSCL_CBA(n->bar.pmrmscl) << PMRMSCL_CBA_SHIFT); > if (cba + int128_get64(n->pmr.dev->mr.size) < cba) { > NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1); > return; >@@ -5936,7 +5937,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, > return; > } > >- n->bar.pmrmsc = (n->bar.pmrmsc & 0xffffffff) | (data << 32); >+ n->bar.pmrmscu = data & 0xffffffff; > return; > default: > NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, >-- >2.32.0 > > Changes LGTM. Reviewed-by: Gollu Appalanaidu ------hb-dvdiRZtWrjeusMudXEerT0TTrvs-OGX_88iZ4NSx451yS=_11c195_ Content-Type: text/plain; charset="utf-8" ------hb-dvdiRZtWrjeusMudXEerT0TTrvs-OGX_88iZ4NSx451yS=_11c195_--