From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 09/12] char: ibex_uart: Update the register layout
Date: Thu, 15 Jul 2021 00:16:37 -0700 [thread overview]
Message-ID: <20210715071640.232070-10-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210715071640.232070-1-alistair.francis@wdc.com>
Update the register layout to match the latest OpenTitan bitstream.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com
---
hw/char/ibex_uart.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index fe4b6c3c9e..6b0c9330bf 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -42,7 +42,8 @@ REG32(INTR_STATE, 0x00)
FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
REG32(INTR_ENABLE, 0x04)
REG32(INTR_TEST, 0x08)
-REG32(CTRL, 0x0C)
+REG32(ALERT_TEST, 0x0C)
+REG32(CTRL, 0x10)
FIELD(CTRL, TX_ENABLE, 0, 1)
FIELD(CTRL, RX_ENABLE, 1, 1)
FIELD(CTRL, NF, 2, 1)
@@ -52,25 +53,25 @@ REG32(CTRL, 0x0C)
FIELD(CTRL, PARITY_ODD, 7, 1)
FIELD(CTRL, RXBLVL, 8, 2)
FIELD(CTRL, NCO, 16, 16)
-REG32(STATUS, 0x10)
+REG32(STATUS, 0x14)
FIELD(STATUS, TXFULL, 0, 1)
FIELD(STATUS, RXFULL, 1, 1)
FIELD(STATUS, TXEMPTY, 2, 1)
FIELD(STATUS, RXIDLE, 4, 1)
FIELD(STATUS, RXEMPTY, 5, 1)
-REG32(RDATA, 0x14)
-REG32(WDATA, 0x18)
-REG32(FIFO_CTRL, 0x1c)
+REG32(RDATA, 0x18)
+REG32(WDATA, 0x1C)
+REG32(FIFO_CTRL, 0x20)
FIELD(FIFO_CTRL, RXRST, 0, 1)
FIELD(FIFO_CTRL, TXRST, 1, 1)
FIELD(FIFO_CTRL, RXILVL, 2, 3)
FIELD(FIFO_CTRL, TXILVL, 5, 2)
-REG32(FIFO_STATUS, 0x20)
+REG32(FIFO_STATUS, 0x24)
FIELD(FIFO_STATUS, TXLVL, 0, 5)
FIELD(FIFO_STATUS, RXLVL, 16, 5)
-REG32(OVRD, 0x24)
-REG32(VAL, 0x28)
-REG32(TIMEOUT_CTRL, 0x2c)
+REG32(OVRD, 0x28)
+REG32(VAL, 0x2C)
+REG32(TIMEOUT_CTRL, 0x30)
static void ibex_uart_update_irqs(IbexUartState *s)
{
--
2.31.1
next prev parent reply other threads:[~2021-07-15 7:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 7:16 [PULL v2 00/12] riscv-to-apply queue Alistair Francis
2021-07-15 7:16 ` [PULL v2 01/12] target/riscv: pmp: Fix some typos Alistair Francis
2021-07-15 7:16 ` [PULL v2 02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines Alistair Francis
2021-07-15 7:16 ` [PULL v2 03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc Alistair Francis
2021-07-15 7:16 ` [PULL v2 04/12] docs/system: riscv: Add documentation for virt machine Alistair Francis
2021-07-15 7:16 ` [PULL v2 05/12] target/riscv: hardwire bits in hideleg and hedeleg Alistair Francis
2021-07-15 7:16 ` [PULL v2 06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot Alistair Francis
2021-07-15 7:16 ` [PULL v2 07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency Alistair Francis
2021-07-15 7:16 ` [PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned Alistair Francis
2021-07-15 7:16 ` Alistair Francis [this message]
2021-07-15 7:16 ` [PULL v2 10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-15 7:16 ` [PULL v2 11/12] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-15 7:16 ` [PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack() Alistair Francis
2021-07-16 9:55 ` [PULL v2 00/12] riscv-to-apply queue Peter Maydell
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