From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: "Bin Meng" <bmeng.cn@gmail.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL v2 01/12] target/riscv: pmp: Fix some typos
Date: Thu, 15 Jul 2021 00:16:29 -0700 [thread overview]
Message-ID: <20210715071640.232070-2-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210715071640.232070-1-alistair.francis@wdc.com>
From: Bin Meng <bmeng.cn@gmail.com>
%s/CSP/CSR
%s/thie/the
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 82ed020b10..54abf42583 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -456,7 +456,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
}
/*
- * Handle a write to a pmpcfg CSP
+ * Handle a write to a pmpcfg CSR
*/
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
target_ulong val)
@@ -483,7 +483,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
/*
- * Handle a read from a pmpcfg CSP
+ * Handle a read from a pmpcfg CSR
*/
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
{
@@ -502,7 +502,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
/*
- * Handle a write to a pmpaddr CSP
+ * Handle a write to a pmpaddr CSR
*/
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val)
@@ -540,7 +540,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
/*
- * Handle a read from a pmpaddr CSP
+ * Handle a read from a pmpaddr CSR
*/
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
{
@@ -593,7 +593,7 @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
/*
* Calculate the TLB size if the start address or the end address of
- * PMP entry is presented in thie TLB page.
+ * PMP entry is presented in the TLB page.
*/
static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
target_ulong tlb_sa, target_ulong tlb_ea)
--
2.31.1
next prev parent reply other threads:[~2021-07-15 7:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 7:16 [PULL v2 00/12] riscv-to-apply queue Alistair Francis
2021-07-15 7:16 ` Alistair Francis [this message]
2021-07-15 7:16 ` [PULL v2 02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines Alistair Francis
2021-07-15 7:16 ` [PULL v2 03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc Alistair Francis
2021-07-15 7:16 ` [PULL v2 04/12] docs/system: riscv: Add documentation for virt machine Alistair Francis
2021-07-15 7:16 ` [PULL v2 05/12] target/riscv: hardwire bits in hideleg and hedeleg Alistair Francis
2021-07-15 7:16 ` [PULL v2 06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot Alistair Francis
2021-07-15 7:16 ` [PULL v2 07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency Alistair Francis
2021-07-15 7:16 ` [PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned Alistair Francis
2021-07-15 7:16 ` [PULL v2 09/12] char: ibex_uart: Update the register layout Alistair Francis
2021-07-15 7:16 ` [PULL v2 10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-15 7:16 ` [PULL v2 11/12] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-15 7:16 ` [PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack() Alistair Francis
2021-07-16 9:55 ` [PULL v2 00/12] riscv-to-apply queue Peter Maydell
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