From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc
Date: Thu, 15 Jul 2021 00:16:31 -0700 [thread overview]
Message-ID: <20210715071640.232070-4-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210715071640.232070-1-alistair.francis@wdc.com>
From: Bin Meng <bmeng.cn@gmail.com>
It's Core *Local* Interruptor, not 'Level'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/sifive_u.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 32d0a1b85d..01108b5ecc 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices:
* 1 E51 / E31 core
* Up to 4 U54 / U34 cores
-* Core Level Interruptor (CLINT)
+* Core Local Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* Power, Reset, Clock, Interrupt (PRCI)
* L2 Loosely Integrated Memory (L2-LIM)
--
2.31.1
next prev parent reply other threads:[~2021-07-15 7:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 7:16 [PULL v2 00/12] riscv-to-apply queue Alistair Francis
2021-07-15 7:16 ` [PULL v2 01/12] target/riscv: pmp: Fix some typos Alistair Francis
2021-07-15 7:16 ` [PULL v2 02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines Alistair Francis
2021-07-15 7:16 ` Alistair Francis [this message]
2021-07-15 7:16 ` [PULL v2 04/12] docs/system: riscv: Add documentation for virt machine Alistair Francis
2021-07-15 7:16 ` [PULL v2 05/12] target/riscv: hardwire bits in hideleg and hedeleg Alistair Francis
2021-07-15 7:16 ` [PULL v2 06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot Alistair Francis
2021-07-15 7:16 ` [PULL v2 07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency Alistair Francis
2021-07-15 7:16 ` [PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned Alistair Francis
2021-07-15 7:16 ` [PULL v2 09/12] char: ibex_uart: Update the register layout Alistair Francis
2021-07-15 7:16 ` [PULL v2 10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-15 7:16 ` [PULL v2 11/12] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-15 7:16 ` [PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack() Alistair Francis
2021-07-16 9:55 ` [PULL v2 00/12] riscv-to-apply queue Peter Maydell
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