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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l23sm4053391wme.22.2021.07.18.05.46.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Jul 2021 05:46:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/12] target/arm: Fix offsets for TTBCR Date: Sun, 18 Jul 2021 13:46:10 +0100 Message-Id: <20210718124621.13395-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210718124621.13395-1-peter.maydell@linaro.org> References: <20210718124621.13395-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The functions vmsa_ttbcr_write and vmsa_ttbcr_raw_write expect the offset to be for the complete TCR structure, not the offset to the low 32-bits of a uint64_t. Using offsetoflow32 in this case breaks big-endian hosts. For TTBCR2, we do want the high 32-bits of a uint64_t. Use cp15.tcr_el[*].raw_tcr as the offsetofhigh32 argument to clarify this. Buglink: https://gitlab.com/qemu-project/qemu/-/issues/187 Signed-off-by: Richard Henderson Message-id: 20210709230621.938821-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 910ace42741..0c07ca98376 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4106,8 +4106,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, .raw_writefn = vmsa_ttbcr_raw_write, - .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), - offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, + /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), + offsetof(CPUARMState, cp15.tcr_el[1])} }, REGINFO_SENTINEL }; @@ -4118,8 +4119,10 @@ static const ARMCPRegInfo ttbcr2_reginfo = { .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, - .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), - offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, + .bank_fieldoffsets = { + offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), + offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), + }, }; static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, -- 2.20.1