From: Alessandro Di Federico via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng,
nizzo@rev.ng, richard.henderson@linaro.org,
Alessandro Di Federico <ale@rev.ng>
Subject: [PATCH v6 04/12] target/hexagon: make helper functions non-static
Date: Tue, 20 Jul 2021 14:30:23 +0200 [thread overview]
Message-ID: <20210720123031.1101682-5-ale.qemu@rev.ng> (raw)
In-Reply-To: <20210720123031.1101682-1-ale.qemu@rev.ng>
From: Paolo Montesel <babush@rev.ng>
Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.
This commit also makes some op_helper.c non-static in order to avoid
having them marked as unused when using the idef-parser generated code.
Signed-off-by: Alessandro Di Federico <ale@rev.ng>
Signed-off-by: Paolo Montesel <babush@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/genptr.h | 30 +++++++++++++++++++
target/hexagon/op_helper.h | 37 ++++++++++++++++++++++++
target/hexagon/genptr.c | 59 +++++++++++++++++++++-----------------
target/hexagon/op_helper.c | 29 +++++++++----------
4 files changed, 113 insertions(+), 42 deletions(-)
create mode 100644 target/hexagon/op_helper.h
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index c158005d2a..d71dd7e1ce 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -19,7 +19,37 @@
#define HEXAGON_GENPTR_H
#include "insn.h"
+#include "tcg/tcg.h"
+#include "translate.h"
extern const SemanticInsn opcode_genptr[];
+void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
+void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ uint32_t slot);
+void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ uint32_t slot);
+void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ uint32_t slot);
+void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *ctx,
+ uint32_t slot);
+void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
+ uint32_t slot);
+void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
+ uint32_t slot);
+void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
+ uint32_t slot);
+void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, DisasContext *ctx,
+ uint32_t slot);
+TCGv gen_read_preg(TCGv pred, uint8_t num);
+void gen_log_reg_write(int rnum, TCGv val);
+void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
+TCGv gen_8bitsof(TCGv result, TCGv value);
+void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
+TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
+TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign);
+TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign);
+void gen_set_half(int N, TCGv result, TCGv src);
+void gen_set_half_i64(int N, TCGv_i64 result, TCGv src);
+
#endif
diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h
new file mode 100644
index 0000000000..2d39637b8f
--- /dev/null
+++ b/target/hexagon/op_helper.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_OP_HELPER_H
+#define HEXAGON_OP_HELPER_H
+
+/* Misc functions */
+void cancel_slot(CPUHexagonState *env, uint32_t slot);
+void write_new_pc(CPUHexagonState *env, target_ulong addr);
+
+uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
+uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
+uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
+uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
+
+void log_reg_write(CPUHexagonState *env, int rnum, target_ulong val,
+ uint32_t slot);
+void log_store64(CPUHexagonState *env, target_ulong addr, int64_t val,
+ int width, int slot);
+void log_store32(CPUHexagonState *env, target_ulong addr, target_ulong val,
+ int width, int slot);
+
+#endif
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 2c7f4136b5..5e7f446657 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -26,6 +26,13 @@
#include "macros.h"
#undef QEMU_GENERATE
#include "gen_tcg.h"
+#include "genptr.h"
+
+TCGv gen_read_preg(TCGv pred, uint8_t num)
+{
+ tcg_gen_mov_tl(pred, hex_pred[num]);
+ return pred;
+}
static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
uint32_t slot)
@@ -52,7 +59,7 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
tcg_temp_free(slot_mask);
}
-static inline void gen_log_reg_write(int rnum, TCGv val)
+void gen_log_reg_write(int rnum, TCGv val)
{
tcg_gen_mov_tl(hex_new_value[rnum], val);
if (HEX_DEBUG) {
@@ -115,7 +122,7 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
}
}
-static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
+void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
{
TCGv base_val = tcg_temp_new();
@@ -255,7 +262,7 @@ static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
}
}
-static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
+TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
{
if (sign) {
tcg_gen_sextract_tl(result, src, N * 8, 8);
@@ -265,7 +272,7 @@ static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
return result;
}
-static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
+TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
{
TCGv_i64 res64 = tcg_temp_new_i64();
if (sign) {
@@ -279,7 +286,7 @@ static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
return result;
}
-static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
+TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
{
if (sign) {
tcg_gen_sextract_tl(result, src, N * 16, 16);
@@ -289,12 +296,12 @@ static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
return result;
}
-static inline void gen_set_half(int N, TCGv result, TCGv src)
+void gen_set_half(int N, TCGv result, TCGv src)
{
tcg_gen_deposit_tl(result, result, src, N * 16, 16);
}
-static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
+void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
{
TCGv_i64 src64 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(src64, src);
@@ -302,7 +309,7 @@ static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
tcg_temp_free_i64(src64);
}
-static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
+void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
{
TCGv_i64 src64 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(src64, src);
@@ -381,60 +388,60 @@ static inline void gen_store_conditional8(DisasContext *ctx,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
-static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
}
-static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, uint32_t slot)
+void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ uint32_t slot)
{
gen_store32(vaddr, src, 1, slot);
ctx->store_width[slot] = 1;
}
-static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, uint32_t slot)
+void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
+ uint32_t slot)
{
TCGv tmp = tcg_const_tl(src);
gen_store1(cpu_env, vaddr, tmp, ctx, slot);
tcg_temp_free(tmp);
}
-static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, uint32_t slot)
+void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ uint32_t slot)
{
gen_store32(vaddr, src, 2, slot);
ctx->store_width[slot] = 2;
}
-static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, uint32_t slot)
+void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
+ uint32_t slot)
{
TCGv tmp = tcg_const_tl(src);
gen_store2(cpu_env, vaddr, tmp, ctx, slot);
tcg_temp_free(tmp);
}
-static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, uint32_t slot)
+void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ uint32_t slot)
{
gen_store32(vaddr, src, 4, slot);
ctx->store_width[slot] = 4;
}
-static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, uint32_t slot)
+void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
+ uint32_t slot)
{
TCGv tmp = tcg_const_tl(src);
gen_store4(cpu_env, vaddr, tmp, ctx, slot);
tcg_temp_free(tmp);
}
-static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
- DisasContext *ctx, uint32_t slot)
+void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *ctx,
+ uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], 8);
@@ -442,15 +449,15 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
ctx->store_width[slot] = 8;
}
-static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
- DisasContext *ctx, uint32_t slot)
+void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, DisasContext *ctx,
+ uint32_t slot)
{
TCGv_i64 tmp = tcg_const_i64(src);
gen_store8(cpu_env, vaddr, tmp, ctx, slot);
tcg_temp_free_i64(tmp);
}
-static TCGv gen_8bitsof(TCGv result, TCGv value)
+TCGv gen_8bitsof(TCGv result, TCGv value)
{
TCGv zero = tcg_const_tl(0);
TCGv ones = tcg_const_tl(0xff);
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 459555966d..a864e68837 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -25,6 +25,7 @@
#include "arch.h"
#include "hex_arch_types.h"
#include "fma_emu.h"
+#include "op_helper.h"
#define SF_BIAS 127
#define SF_MANTBITS 23
@@ -45,8 +46,8 @@ void QEMU_NORETURN HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp)
do_raise_exception_err(env, excp, 0);
}
-static void log_reg_write(CPUHexagonState *env, int rnum,
- target_ulong val, uint32_t slot)
+void log_reg_write(CPUHexagonState *env, int rnum, target_ulong val,
+ uint32_t slot)
{
HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")",
rnum, val, val);
@@ -77,8 +78,8 @@ static void log_pred_write(CPUHexagonState *env, int pnum, target_ulong val)
}
}
-static void log_store32(CPUHexagonState *env, target_ulong addr,
- target_ulong val, int width, int slot)
+void log_store32(CPUHexagonState *env, target_ulong addr, target_ulong val,
+ int width, int slot)
{
HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx
", %" PRId32 " [0x08%" PRIx32 "])\n",
@@ -88,8 +89,8 @@ static void log_store32(CPUHexagonState *env, target_ulong addr,
env->mem_log_stores[slot].data32 = val;
}
-static void log_store64(CPUHexagonState *env, target_ulong addr,
- int64_t val, int width, int slot)
+void log_store64(CPUHexagonState *env, target_ulong addr, int64_t val,
+ int width, int slot)
{
HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx
", %" PRId64 " [0x016%" PRIx64 "])\n",
@@ -99,7 +100,7 @@ static void log_store64(CPUHexagonState *env, target_ulong addr,
env->mem_log_stores[slot].data64 = val;
}
-static void write_new_pc(CPUHexagonState *env, target_ulong addr)
+void write_new_pc(CPUHexagonState *env, target_ulong addr)
{
HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr);
@@ -390,8 +391,7 @@ static void check_noshuf(CPUHexagonState *env, uint32_t slot)
}
}
-static uint8_t mem_load1(CPUHexagonState *env, uint32_t slot,
- target_ulong vaddr)
+uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
{
uint8_t retval;
check_noshuf(env, slot);
@@ -399,8 +399,7 @@ static uint8_t mem_load1(CPUHexagonState *env, uint32_t slot,
return retval;
}
-static uint16_t mem_load2(CPUHexagonState *env, uint32_t slot,
- target_ulong vaddr)
+uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
{
uint16_t retval;
check_noshuf(env, slot);
@@ -408,8 +407,7 @@ static uint16_t mem_load2(CPUHexagonState *env, uint32_t slot,
return retval;
}
-static uint32_t mem_load4(CPUHexagonState *env, uint32_t slot,
- target_ulong vaddr)
+uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
{
uint32_t retval;
check_noshuf(env, slot);
@@ -417,8 +415,7 @@ static uint32_t mem_load4(CPUHexagonState *env, uint32_t slot,
return retval;
}
-static uint64_t mem_load8(CPUHexagonState *env, uint32_t slot,
- target_ulong vaddr)
+uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
{
uint64_t retval;
check_noshuf(env, slot);
@@ -1167,7 +1164,7 @@ float64 HELPER(dfmpyhh)(CPUHexagonState *env, float64 RxxV,
return RxxV;
}
-static void cancel_slot(CPUHexagonState *env, uint32_t slot)
+void cancel_slot(CPUHexagonState *env, uint32_t slot)
{
HEX_DEBUG_LOG("Slot %d cancelled\n", slot);
env->slot_cancelled |= (1 << slot);
--
2.32.0
next prev parent reply other threads:[~2021-07-20 12:36 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 12:30 [PATCH v6 00/12] target/hexagon: introduce idef-parser Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 01/12] target/hexagon: update MAINTAINERS for idef-parser Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 02/12] target/hexagon: import README " Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 03/12] target/hexagon: make slot number an unsigned Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-07-20 12:30 ` Alessandro Di Federico via [this message]
2021-07-20 12:30 ` [PATCH v6 05/12] target/hexagon: introduce new helper functions Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 06/12] target/hexagon: expose next PC in DisasContext Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 07/12] target/hexagon: prepare input for the idef-parser Alessandro Di Federico via
2021-09-07 18:09 ` Taylor Simpson
2021-10-18 11:23 ` Anton Johansson via
2021-10-28 15:44 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 08/12] target/hexagon: import lexer for idef-parser Alessandro Di Federico via
2021-09-07 18:08 ` Taylor Simpson
2021-10-18 11:37 ` Anton Johansson via
2021-10-28 15:49 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 09/12] target/hexagon: import parser " Alessandro Di Federico via
2021-09-07 18:08 ` Taylor Simpson
2021-09-08 6:35 ` Richard Henderson
2021-10-18 11:42 ` Anton Johansson via
2021-10-28 15:56 ` Taylor Simpson
2021-07-20 12:30 ` [PATCH v6 10/12] target/hexagon: call idef-parser functions Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 11/12] target/hexagon: import additional tests Alessandro Di Federico via
2021-07-20 12:30 ` [PATCH v6 12/12] gitlab-ci: do not use qemu-project Docker registry Alessandro Di Federico via
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