* [PATCH] target/riscv: Add User CSRs read-only check
@ 2021-08-09 7:07 LIU Zhiwei
2021-08-09 9:35 ` Bin Meng
0 siblings, 1 reply; 6+ messages in thread
From: LIU Zhiwei @ 2021-08-09 7:07 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a4ed18ac5..ea62d9e653 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
RISCVException ret;
target_ulong old_value;
RISCVCPU *cpu = env_archcpu(env);
+ int read_only = get_field(csrno, 0xC00) == 3;
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
- int read_only = get_field(csrno, 0xC00) == 3;
if (riscv_has_ext(env, RVH) &&
env->priv == PRV_S &&
@@ -1443,6 +1443,10 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
return RISCV_EXCP_ILLEGAL_INST;
}
+#else
+ if (write_mask && read_only) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
#endif
/* ensure the CSR extension is enabled. */
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Add User CSRs read-only check
2021-08-09 7:07 [PATCH] target/riscv: Add User CSRs read-only check LIU Zhiwei
@ 2021-08-09 9:35 ` Bin Meng
2021-08-09 9:43 ` LIU Zhiwei
0 siblings, 1 reply; 6+ messages in thread
From: Bin Meng @ 2021-08-09 9:35 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Mon, Aug 9, 2021 at 3:09 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
nits: please write something in the commit message
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9a4ed18ac5..ea62d9e653 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> RISCVException ret;
> target_ulong old_value;
> RISCVCPU *cpu = env_archcpu(env);
> + int read_only = get_field(csrno, 0xC00) == 3;
>
> /* check privileges and return -1 if check fails */
> #if !defined(CONFIG_USER_ONLY)
> int effective_priv = env->priv;
> - int read_only = get_field(csrno, 0xC00) == 3;
>
> if (riscv_has_ext(env, RVH) &&
> env->priv == PRV_S &&
> @@ -1443,6 +1443,10 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> +#else
> + if (write_mask && read_only) {
This can be merged by the !CONFIG_USER_ONLY case.
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> #endif
>
> /* ensure the CSR extension is enabled. */
Regards,
Bin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Add User CSRs read-only check
2021-08-09 9:35 ` Bin Meng
@ 2021-08-09 9:43 ` LIU Zhiwei
2021-08-09 9:49 ` Bin Meng
0 siblings, 1 reply; 6+ messages in thread
From: LIU Zhiwei @ 2021-08-09 9:43 UTC (permalink / raw)
To: Bin Meng
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On 2021/8/9 下午5:35, Bin Meng wrote:
> On Mon, Aug 9, 2021 at 3:09 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> nits: please write something in the commit message
OK
>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/csr.c | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 9a4ed18ac5..ea62d9e653 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
>> RISCVException ret;
>> target_ulong old_value;
>> RISCVCPU *cpu = env_archcpu(env);
>> + int read_only = get_field(csrno, 0xC00) == 3;
>>
>> /* check privileges and return -1 if check fails */
>> #if !defined(CONFIG_USER_ONLY)
>> int effective_priv = env->priv;
>> - int read_only = get_field(csrno, 0xC00) == 3;
>>
>> if (riscv_has_ext(env, RVH) &&
>> env->priv == PRV_S &&
>> @@ -1443,6 +1443,10 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
>> (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
>> return RISCV_EXCP_ILLEGAL_INST;
>> }
>> +#else
>> + if (write_mask && read_only) {
> This can be merged by the !CONFIG_USER_ONLY case.
Do you mean
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
return -RISCV_EXCP_ILLEGAL_INST;
}
#else
if (write_mask && read_only) {
return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
Thanks,
Zhiwei
>
>> + return -RISCV_EXCP_ILLEGAL_INST;
>> + }
>> #endif
>>
>> /* ensure the CSR extension is enabled. */
> Regards,
> Bin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Add User CSRs read-only check
2021-08-09 9:43 ` LIU Zhiwei
@ 2021-08-09 9:49 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2021-08-09 9:49 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Mon, Aug 9, 2021 at 5:45 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2021/8/9 下午5:35, Bin Meng wrote:
> > On Mon, Aug 9, 2021 at 3:09 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> > nits: please write something in the commit message
> OK
> >
> >> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> >> ---
> >> target/riscv/csr.c | 6 +++++-
> >> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> >> index 9a4ed18ac5..ea62d9e653 100644
> >> --- a/target/riscv/csr.c
> >> +++ b/target/riscv/csr.c
> >> @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> >> RISCVException ret;
> >> target_ulong old_value;
> >> RISCVCPU *cpu = env_archcpu(env);
> >> + int read_only = get_field(csrno, 0xC00) == 3;
> >>
> >> /* check privileges and return -1 if check fails */
> >> #if !defined(CONFIG_USER_ONLY)
> >> int effective_priv = env->priv;
> >> - int read_only = get_field(csrno, 0xC00) == 3;
> >>
> >> if (riscv_has_ext(env, RVH) &&
> >> env->priv == PRV_S &&
> >> @@ -1443,6 +1443,10 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> >> (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
> >> return RISCV_EXCP_ILLEGAL_INST;
> >> }
> >> +#else
> >> + if (write_mask && read_only) {
> > This can be merged by the !CONFIG_USER_ONLY case.
>
> Do you mean
>
> #if !defined(CONFIG_USER_ONLY)
> if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
> return -RISCV_EXCP_ILLEGAL_INST;
> }
> #else
Should be #endif
> if (write_mask && read_only) {
> return -RISCV_EXCP_ILLEGAL_INST;
> }
>
> #endif
and drop this #endif
Regards,
Bin
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] target/riscv: Add User CSRs read-only check
@ 2021-08-09 10:32 LIU Zhiwei
2021-08-09 10:39 ` Bin Meng
0 siblings, 1 reply; 6+ messages in thread
From: LIU Zhiwei @ 2021-08-09 10:32 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis, LIU Zhiwei
For U-mode CSRs, read-only check is also needed.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a4ed18ac5..360e4bfa33 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
RISCVException ret;
target_ulong old_value;
RISCVCPU *cpu = env_archcpu(env);
+ int read_only = get_field(csrno, 0xC00) == 3;
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
- int read_only = get_field(csrno, 0xC00) == 3;
if (riscv_has_ext(env, RVH) &&
env->priv == PRV_S &&
@@ -1439,11 +1439,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
effective_priv++;
}
- if ((write_mask && read_only) ||
- (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
+ if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
+ if (write_mask && read_only) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Add User CSRs read-only check
2021-08-09 10:32 LIU Zhiwei
@ 2021-08-09 10:39 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2021-08-09 10:39 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Mon, Aug 9, 2021 at 6:37 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> For U-mode CSRs, read-only check is also needed.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9a4ed18ac5..360e4bfa33 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> RISCVException ret;
> target_ulong old_value;
> RISCVCPU *cpu = env_archcpu(env);
> + int read_only = get_field(csrno, 0xC00) == 3;
>
> /* check privileges and return -1 if check fails */
> #if !defined(CONFIG_USER_ONLY)
> int effective_priv = env->priv;
> - int read_only = get_field(csrno, 0xC00) == 3;
>
> if (riscv_has_ext(env, RVH) &&
> env->priv == PRV_S &&
> @@ -1439,11 +1439,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> effective_priv++;
> }
>
> - if ((write_mask && read_only) ||
> - (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
> + if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> #endif
> + if (write_mask && read_only) {
> + return -RISCV_EXCP_ILLEGAL_INST;
This should be RISCV_EXCP_ILLEGAL_INST
> + }
>
> /* ensure the CSR extension is enabled. */
> if (!cpu->cfg.ext_icsr) {
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-08-09 10:40 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-08-09 7:07 [PATCH] target/riscv: Add User CSRs read-only check LIU Zhiwei
2021-08-09 9:35 ` Bin Meng
2021-08-09 9:43 ` LIU Zhiwei
2021-08-09 9:49 ` Bin Meng
-- strict thread matches above, loose matches on Subject: below --
2021-08-09 10:32 LIU Zhiwei
2021-08-09 10:39 ` Bin Meng
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).