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Mon, 09 Aug 2021 06:11:46 -0700 (PDT) Received: from rekt.ibmuc.com ([191.19.172.190]) by smtp.gmail.com with ESMTPSA id f3sm6757435qti.65.2021.08.09.06.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 06:11:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 16/19] target/ppc/pmu_book3s_helper: adding 0xFA event Date: Mon, 9 Aug 2021 10:10:54 -0300 Message-Id: <20210809131057.1694145-17-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The PowerISA 3.1 defines the 0xFA event as instructions completed when the thread's CTRL register is set. Some EBB powerpc kernel tests use this event to exercise both the PMU and the EBB support. We don't have a way at this moment to tell whether an instruction was completed under those conditions. What we can do is to make it equivalent to the existing PM_INST_COMPL event that counts all instructions completed. For our current purposes with the PMU support this is enough. Signed-off-by: Daniel Henrique Barboza --- target/ppc/pmu_book3s_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index c5c5ab38c9..388263688b 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -52,6 +52,20 @@ static uint8_t get_PMC_event(CPUPPCState *env, int sprn) break; case SPR_POWER_PMC4: event = MMCR1_PMC4SEL & env->spr[SPR_POWER_MMCR1]; + + /* + * Event 0xFA for PMC4SEL is described as follows in + * PowerISA v3.1: + * + * "The thread has completed an instruction when the RUN bit of + * the thread’s CTRL register contained 1" + * + * Our closest equivalent for this event at this moment is plain + * INST_CMPL (event 0x2) + */ + if (event == 0xFA) { + event = 0x2; + } break; case SPR_POWER_PMC5: event = 0x2; -- 2.31.1