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Mon, 09 Aug 2021 06:11:49 -0700 (PDT) Received: from rekt.ibmuc.com ([191.19.172.190]) by smtp.gmail.com with ESMTPSA id f3sm6757435qti.65.2021.08.09.06.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 06:11:49 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 17/19] target/ppc/pmu_book3s_helper.c: add PMC14/PMC56 counter freeze bits Date: Mon, 9 Aug 2021 10:10:55 -0300 Message-Id: <20210809131057.1694145-18-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x736.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We're missing two counter freeze bits that are used to further control how the PMCs behaves: MMCR0_FC14 and MMCR0_FC56. These bits can frozen PMCs separately: MMCR0_FC14 freezes PMCs 1 to 4 and MMCR0_FC56 freezes PMCs 5 and 6. The EBB powerpc kernel test 'pmc56_overflow' exercises this logic. Let's add it in the PMU logic to make this test pass. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 2 ++ target/ppc/pmu_book3s_helper.c | 23 +++++++++++++++++------ 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1aa1fd42af..204f0d58ee 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -352,6 +352,8 @@ typedef struct ppc_v3_pate_t { #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ #define MMCR0_PMC1CE PPC_BIT(48) #define MMCR0_PMCjCE PPC_BIT(49) +#define MMCR0_FC14 PPC_BIT(58) +#define MMCR0_FC56 PPC_BIT(59) #define MMCR1_PMC1SEL_SHIFT (63 - 39) #define MMCR1_PMC1SEL PPC_BITMASK(32, 39) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 388263688b..ae7050cd62 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -115,14 +115,20 @@ static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, */ static void update_PMCs(CPUPPCState *env, uint64_t icount_delta) { + bool PMC14_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14); + bool PMC56_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); int sprn; - for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { - update_programmable_PMC_reg(env, sprn, icount_delta); + if (PMC14_running) { + for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { + update_programmable_PMC_reg(env, sprn, icount_delta); + } } - update_PMC_PM_INST_CMPL(env, SPR_POWER_PMC5, icount_delta); - update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); + if (PMC56_running) { + update_PMC_PM_INST_CMPL(env, SPR_POWER_PMC5, icount_delta); + update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); + } } static int64_t get_INST_CMPL_timeout(CPUPPCState *env, int sprn) @@ -159,16 +165,21 @@ static int64_t get_CYC_timeout(CPUPPCState *env, int sprn) static bool pmc_counter_negative_enabled(CPUPPCState *env, int sprn) { + bool PMC14_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14); + bool PMC56_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); + switch (sprn) { case SPR_POWER_PMC1: - return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE && PMC14_running; case SPR_POWER_PMC2: case SPR_POWER_PMC3: case SPR_POWER_PMC4: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE && PMC14_running; + case SPR_POWER_PMC5: case SPR_POWER_PMC6: - return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE && PMC56_running; default: break; -- 2.31.1