From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: gustavo.romero@linaro.org,
Daniel Henrique Barboza <danielhb413@gmail.com>,
groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org,
david@gibson.dropbear.id.au
Subject: [PATCH 01/19] target/ppc: add exclusive Book3S PMU reg read/write functions
Date: Mon, 9 Aug 2021 10:10:39 -0300 [thread overview]
Message-ID: <20210809131057.1694145-2-danielhb413@gmail.com> (raw)
In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com>
The PowerPC PMU, as described by PowerISA v3.1, has a lot of functions
that freezes, resets and sets counters to specific values depending on
the circuntances. Some of these are trigged based on read/value of the
PMU registers (MMCR0, MMCR1, MMCR2, MMCRA and PMC counters).
Having to handle the PMU logic using the generic read/write functions
can impact all other registers that has nothing to do with the PMU that
uses these functions. This patch creates two new functions,
spr_read_pmu_generic() and spr_write_pmu_generic, that will be used later
on to handle PMU logic together with the read/write of PMU registers.
We're not ready to add specific PMU logic in these new functions yet, so
for now these are just stubs that calls spr_read/write_generic(). No
functional change is made.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu_init.c | 24 ++++++++++++------------
target/ppc/spr_tcg.h | 2 ++
target/ppc/translate.c | 12 ++++++++++++
3 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 505a0ed6ac..021c1bc750 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6821,47 +6821,47 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_MMCR0, 0x00000000);
spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_MMCR1, 0x00000000);
spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_MMCRA, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_PMC1, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_PMC2, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_PMC3, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_PMC4, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, spr_write_pmu_generic,
KVM_REG_PPC_PMC5, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_PMC6, 0x00000000);
spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_SIAR, 0x00000000);
spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_SDAR, 0x00000000);
}
@@ -6941,7 +6941,7 @@ static void register_power8_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_pmu_generic, &spr_write_pmu_generic,
KVM_REG_PPC_MMCR2, 0x00000000);
spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 0be5f347d5..2aab5878a0 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -25,6 +25,8 @@
void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
+void spr_read_pmu_generic(DisasContext *ctx, int gprn, int sprn);
+void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 171b216e17..c8f3878002 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -385,6 +385,12 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
spr_load_dump_spr(sprn);
}
+void spr_read_pmu_generic(DisasContext *ctx, int gprn, int sprn)
+{
+ /* For now it's just a call to spr_read_generic() */
+ spr_read_generic(ctx, gprn, sprn);
+}
+
static void spr_store_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
@@ -400,6 +406,12 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
spr_store_dump_spr(sprn);
}
+void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn)
+{
+ /* For now it's just a call to spr_write_generic() */
+ spr_write_generic(ctx, sprn, gprn);
+}
+
#if !defined(CONFIG_USER_ONLY)
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
{
--
2.31.1
next prev parent reply other threads:[~2021-08-09 13:13 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-09 13:10 [PATCH 00/19] PMU-EBB support for PPC64 TCG Daniel Henrique Barboza
2021-08-09 13:10 ` Daniel Henrique Barboza [this message]
2021-08-10 3:19 ` [PATCH 01/19] target/ppc: add exclusive Book3S PMU reg read/write functions David Gibson
2021-08-10 13:06 ` Daniel Henrique Barboza
2021-08-09 13:10 ` [PATCH 02/19] target/ppc: add exclusive user read function for PMU regs Daniel Henrique Barboza
2021-08-10 3:21 ` David Gibson
2021-08-09 13:10 ` [PATCH 03/19] target/ppc: add exclusive user write " Daniel Henrique Barboza
2021-08-10 3:29 ` David Gibson
2021-08-11 0:05 ` Richard Henderson
2021-08-09 13:10 ` [PATCH 04/19] target/ppc: PMU Book3s basic insns count for pseries TCG Daniel Henrique Barboza
2021-08-10 3:39 ` David Gibson
2021-08-10 13:24 ` Daniel Henrique Barboza
2021-08-16 17:53 ` Daniel Henrique Barboza
2021-08-17 2:59 ` David Gibson
2021-08-17 9:30 ` Daniel Henrique Barboza
2021-08-18 5:48 ` David Gibson
2021-08-11 0:26 ` Richard Henderson
2021-08-09 13:10 ` [PATCH 05/19] target/ppc/pmu_book3s_helper.c: eliminate code repetition Daniel Henrique Barboza
2021-08-10 3:40 ` David Gibson
2021-08-09 13:10 ` [PATCH 06/19] target/ppc/pmu_book3s_helper: enable PMC1-PMC4 events Daniel Henrique Barboza
2021-08-10 3:42 ` David Gibson
2021-08-10 15:03 ` Daniel Henrique Barboza
2021-08-10 23:08 ` Daniel Henrique Barboza
2021-08-11 23:27 ` Daniel Henrique Barboza
2021-08-12 1:52 ` David Gibson
2021-08-11 3:32 ` David Gibson
2021-08-09 13:10 ` [PATCH 07/19] target/ppc/pmu_book3s_helper.c: icount fine tuning Daniel Henrique Barboza
2021-08-09 13:10 ` [PATCH 08/19] target/ppc/pmu_book3s_helper.c: do an actual cycles calculation Daniel Henrique Barboza
2021-08-11 0:34 ` Richard Henderson
2021-08-09 13:10 ` [PATCH 09/19] PPC64/TCG: Implement 'rfebb' instruction Daniel Henrique Barboza
2021-08-10 3:50 ` David Gibson
2021-08-10 19:32 ` Daniel Henrique Barboza
2021-08-11 0:42 ` Richard Henderson
2021-08-11 3:36 ` David Gibson
2021-08-11 0:41 ` Richard Henderson
2021-08-09 13:10 ` [PATCH 10/19] target/ppc: PMU Event-Based exception support Daniel Henrique Barboza
2021-08-10 3:55 ` David Gibson
2021-08-11 0:50 ` Richard Henderson
2021-08-09 13:10 ` [PATCH 11/19] target/ppc/excp_helper.c: POWERPC_EXCP_EBB adjustments Daniel Henrique Barboza
2021-08-09 13:10 ` [PATCH 12/19] target/ppc/pmu_book3s_helper.c: enable PMC1 counter negative EBB Daniel Henrique Barboza
2021-08-10 4:01 ` David Gibson
2021-08-10 20:26 ` Daniel Henrique Barboza
2021-08-11 3:40 ` David Gibson
2021-08-11 11:18 ` Daniel Henrique Barboza
2021-08-12 3:39 ` David Gibson
2021-08-12 4:45 ` Richard Henderson
2021-08-12 4:56 ` Richard Henderson
2021-08-12 10:17 ` Daniel Henrique Barboza
2021-08-12 21:24 ` Daniel Henrique Barboza
2021-08-13 0:35 ` Richard Henderson
2021-08-14 19:13 ` Daniel Henrique Barboza
2021-08-15 19:24 ` Richard Henderson
2021-08-09 13:10 ` [PATCH 13/19] target/ppc/translate: PMU: handle setting of PMCs while running Daniel Henrique Barboza
2021-08-10 4:06 ` David Gibson
2021-08-10 20:44 ` Daniel Henrique Barboza
2021-08-11 3:46 ` David Gibson
2021-08-09 13:10 ` [PATCH 14/19] target/ppc/pmu_book3s_helper.c: add generic timeout helpers Daniel Henrique Barboza
2021-08-10 4:09 ` David Gibson
2021-08-09 13:10 ` [PATCH 15/19] target/ppc/pmu_book3s_helper: enable counter negative for all PMCs Daniel Henrique Barboza
2021-08-10 4:11 ` David Gibson
2021-08-10 21:02 ` Daniel Henrique Barboza
2021-08-12 1:44 ` David Gibson
2021-08-09 13:10 ` [PATCH 16/19] target/ppc/pmu_book3s_helper: adding 0xFA event Daniel Henrique Barboza
2021-08-10 4:13 ` David Gibson
2021-08-09 13:10 ` [PATCH 17/19] target/ppc/pmu_book3s_helper.c: add PMC14/PMC56 counter freeze bits Daniel Henrique Barboza
2021-08-09 13:10 ` [PATCH 18/19] target/ppc/pmu_book3s_helper.c: add PM_CMPLU_STALL mock events Daniel Henrique Barboza
2021-08-10 4:17 ` David Gibson
2021-08-10 19:48 ` Daniel Henrique Barboza
2021-08-11 3:37 ` David Gibson
2021-08-09 13:10 ` [PATCH 19/19] docs/specs: add PPC64 TCG PMU-EBB documentation Daniel Henrique Barboza
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