[PATCH 08/19] target/ppc/pmu_book3s_helper.c: do an actual cycles calculation

[Daniel Henrique Barboza <danielhb413@gmail.com>]

We've been considering that PM_CYC is always 4x the number of
instructions sampled. This is not accurate due to several reasons,
including icount shift.

Replace it with a more accurate logic that returns the elapsed cycle
count of the sampled period, based on what the ARM CPU already does in
target/arm/helper.c, cycles_get_count(). Multiply the amount of ns passed
in the icount period (which considers icount shift) with the CPU frequency.

The PPC CPU clock frequency has different values depending on the CPU
implementation. We're defaulting it to 1GHz since it's the same value
used by PNV and pSeries CPUs.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
 target/ppc/pmu_book3s_helper.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c
index 6292b96db9..91bb82e699 100644
--- a/target/ppc/pmu_book3s_helper.c
+++ b/target/ppc/pmu_book3s_helper.c
@@ -17,11 +17,16 @@
 #include "qemu/error-report.h"
 #include "qemu/main-loop.h"
 
+/*
+ * Set arbitrarily based on clock-frequency values used in PNV
+ * and SPAPR code.
+ */
+#define PPC_CPU_FREQ 1000000000
 
 static uint64_t get_cycles(uint64_t icount_delta)
 {
-    /* Placeholder value */
-    return icount_delta * 4;
+    return muldiv64(icount_to_ns(icount_delta), PPC_CPU_FREQ,
+                    NANOSECONDS_PER_SECOND);
 }
 
 static void update_PMC_PM_INST_CMPL(CPUPPCState *env, int sprn,
-- 
2.31.1