[PATCH 0/2] target/arm: Implement remaining HSTR functionality

[Peter Maydell <peter.maydell@linaro.org>]

I was going through some old todo items from years back, and one of
them was "implement HSTR traps".  We actually already do the
interesting part of this (traps of coprocessor register access), but
there are a couple of small loose ends: v7A (but not v8A!) defines
HSTR.TTEE and HSTR.TJDBX trap bits for trapping various bits of the
trivial Thumb2EE and Jazelle implementation.

The documentation for this is in the v7A Arm ARM DDI0406C.d, section
B1.14.10 and B1.14.11, but the summary is that these bits trap from
NS EL0/EL1 to Hyp mode for:
 * TEECR and TEEHBR accesses
 * JOSCR or JMCR sysreg accesses
 * execution of the BXJ insn

This patchset implements the last of the HSTR functionality,
just so I can cross it off my todo list. I don't expect anybody
to actually be using this :-)

thanks
-- PMM

Peter Maydell (2):
  target/arm: Implement HSTR.TTEE
  target/arm: Implement HSTR.TJDBX

 target/arm/cpu.h       |  3 +++
 target/arm/helper.h    |  2 ++
 target/arm/syndrome.h  |  7 +++++++
 target/arm/helper.c    | 35 +++++++++++++++++++++++++++++++++--
 target/arm/op_helper.c | 16 ++++++++++++++++
 target/arm/translate.c | 12 ++++++++++++
 6 files changed, 73 insertions(+), 2 deletions(-)

-- 
2.20.1