From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com
Subject: [PATCH v2 00/21] target/riscv: Use tcg_constant_*
Date: Tue, 17 Aug 2021 11:17:42 -1000 [thread overview]
Message-ID: <20210817211803.283639-1-richard.henderson@linaro.org> (raw)
Replace use of tcg_const_*, which makes a copy into a temp
which must be freed, with direct use of the constant.
Reorg handling of $zero, with different accessors for
source and destination.
Reorg handling of csrs, passing the actual write_mask
instead of a regno.
Use more helpers for RVH expansion.
Changes for v2:
* Retain the requirement to call gen_set_gpr.
* Add DisasExtend as an argument to get_gpr, and ctx->w as a member
of DisasContext. This should help in implementing UXL, where we
should be able to set ctx->w for all insns, but there is certainly
more required for that.
Because of this, I've dropped most of the r-b from v1.
r~
Richard Henderson (21):
target/riscv: Use tcg_constant_*
target/riscv: Clean up division helpers
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
target/riscv: Introduce DisasExtend and new helpers
target/riscv: Add DisasExtend to gen_arith*
target/riscv: Remove gen_arith_div*
target/riscv: Use gen_arith for mulh and mulhu
target/riscv: Move gen_* helpers for RVM
target/riscv: Move gen_* helpers for RVB
target/riscv: Add DisasExtend to gen_unary
target/riscv: Use DisasExtend in shift operations
target/riscv: Add gen_greviw
target/riscv: Use get_gpr in branches
target/riscv: Use {get,dest}_gpr for integer load/store
target/riscv: Reorg csr instructions
target/riscv: Use {get,dest}_gpr for RVA
target/riscv: Use gen_shift_imm_fn for slli_uw
target/riscv: Use {get,dest}_gpr for RVF
target/riscv: Use {get,dest}_gpr for RVD
target/riscv: Tidy trans_rvh.c.inc
target/riscv: Use {get,dest}_gpr for RVV
target/riscv/helper.h | 6 +-
target/riscv/insn32.decode | 1 +
target/riscv/op_helper.c | 18 +-
target/riscv/translate.c | 702 +++++-------------------
target/riscv/insn_trans/trans_rva.c.inc | 51 +-
target/riscv/insn_trans/trans_rvb.c.inc | 382 ++++++++++---
target/riscv/insn_trans/trans_rvd.c.inc | 127 ++---
target/riscv/insn_trans/trans_rvf.c.inc | 149 +++--
target/riscv/insn_trans/trans_rvh.c.inc | 266 ++-------
target/riscv/insn_trans/trans_rvi.c.inc | 360 ++++++------
target/riscv/insn_trans/trans_rvm.c.inc | 176 ++++--
target/riscv/insn_trans/trans_rvv.c.inc | 151 ++---
12 files changed, 1058 insertions(+), 1331 deletions(-)
--
2.25.1
next reply other threads:[~2021-08-17 21:19 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-17 21:17 Richard Henderson [this message]
2021-08-17 21:17 ` [PATCH v2 01/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-18 7:23 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 02/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-18 9:20 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-17 22:15 ` Philippe Mathieu-Daudé
2021-08-18 9:27 ` Bin Meng
2021-08-19 6:20 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-18 10:58 ` Bin Meng
2021-08-19 1:16 ` Richard Henderson
2021-08-19 2:01 ` Richard Henderson
2021-08-19 6:25 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-19 2:42 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 06/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-19 2:43 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-19 3:03 ` Bin Meng
2021-08-19 6:29 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-17 22:19 ` Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-17 22:20 ` Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-17 21:17 ` [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-19 6:13 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 12/21] target/riscv: Add gen_greviw Richard Henderson
2021-08-17 21:17 ` [PATCH v2 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-19 6:19 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-19 6:22 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-19 7:08 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-17 21:18 ` [PATCH v2 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-17 22:24 ` Philippe Mathieu-Daudé
2021-08-17 21:18 ` [PATCH v2 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
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