From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com
Subject: [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM
Date: Tue, 17 Aug 2021 11:17:50 -1000 [thread overview]
Message-ID: <20210817211803.283639-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210817211803.283639-1-richard.henderson@linaro.org>
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvm.c.inc.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 112 ------------------------
target/riscv/insn_trans/trans_rvm.c.inc | 112 ++++++++++++++++++++++++
2 files changed, 112 insertions(+), 112 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e337dca01b..168274934d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -248,118 +248,6 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
}
}
-static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv rl = tcg_temp_new();
- TCGv rh = tcg_temp_new();
-
- tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
- /* fix up for one negative */
- tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
- tcg_gen_and_tl(rl, rl, arg2);
- tcg_gen_sub_tl(ret, rh, rl);
-
- tcg_temp_free(rl);
- tcg_temp_free(rh);
-}
-
-static void gen_div(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp1, temp2, zero, one, mone, min;
-
- /*
- * Handle by altering args to tcg_gen_div to produce req'd results:
- * For overflow: want source1 in temp1 and 1 in temp2
- * For div by zero: want -1 in temp1 and 1 in temp2 -> -1 result
- */
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
- mone = tcg_constant_tl(-1);
- min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
-
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
- tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
- tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
- tcg_gen_or_tl(temp2, temp2, temp1); /* temp2 = overflow | div0 */
-
- /* if div by zero, set source1 to -1, otherwise don't change */
- tcg_gen_movcond_tl(TCG_COND_NE, temp1, source2, zero, source1, mone);
-
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_movcond_tl(TCG_COND_EQ, temp2, temp2, zero, source2, one);
-
- tcg_gen_div_tl(ret, temp1, temp2);
-
- tcg_temp_free(temp1);
- tcg_temp_free(temp2);
-}
-
-static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp1, temp2, zero, one, mone;
-
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
- mone = tcg_constant_tl(-1);
-
- tcg_gen_movcond_tl(TCG_COND_NE, temp1, source2, zero, source1, mone);
- tcg_gen_movcond_tl(TCG_COND_NE, temp2, source2, zero, source2, one);
- tcg_gen_divu_tl(ret, temp1, temp2);
-
- tcg_temp_free(temp1);
- tcg_temp_free(temp2);
-}
-
-static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp1, temp2, zero, one, mone, min;
-
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
- mone = tcg_constant_tl(-1);
- min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
-
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
- tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
- tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, source2, 0); /* temp2 = div0 */
- tcg_gen_or_tl(temp2, temp2, temp1); /* temp2 = overflow | div0 */
-
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_movcond_tl(TCG_COND_EQ, temp2, temp2, zero, source2, one);
- tcg_gen_rem_tl(temp1, temp1, temp2);
-
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_NE, ret, source2, zero, temp1, source1);
-
- tcg_temp_free(temp1);
- tcg_temp_free(temp2);
-}
-
-static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
-{
- TCGv temp2, zero, one;
-
- temp2 = tcg_temp_new();
- zero = tcg_constant_tl(0);
- one = tcg_constant_tl(1);
-
- tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, source2, one);
- tcg_gen_remu_tl(temp2, source1, temp2);
-
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_NE, ret, source2, zero, temp2, source1);
-
- tcg_temp_free(temp2);
-}
-
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 80552be7a3..ca665b96b1 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -39,6 +39,21 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
return gen_arith(ctx, a, EXT_NONE, gen_mulh);
}
+static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv rl = tcg_temp_new();
+ TCGv rh = tcg_temp_new();
+
+ tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
+ /* fix up for one negative */
+ tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
+ tcg_gen_and_tl(rl, rl, arg2);
+ tcg_gen_sub_tl(ret, rh, rl);
+
+ tcg_temp_free(rl);
+ tcg_temp_free(rh);
+}
+
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
@@ -59,18 +74,115 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
}
+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp1, temp2, zero, one, mone, min;
+
+ /*
+ * Handle by altering args to tcg_gen_div to produce req'd results:
+ * For overflow: want source1 in temp1 and 1 in temp2
+ * For div by zero: want -1 in temp1 and 1 in temp2 -> -1 result
+ */
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+ min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+ tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
+ tcg_gen_or_tl(temp2, temp2, temp1); /* temp2 = overflow | div0 */
+
+ /* if div by zero, set source1 to -1, otherwise don't change */
+ tcg_gen_movcond_tl(TCG_COND_NE, temp1, source2, zero, source1, mone);
+
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, temp2, zero, source2, one);
+
+ tcg_gen_div_tl(ret, temp1, temp2);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+}
+
static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_SIGN, gen_div);
}
+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp1, temp2, zero, one, mone;
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+
+ tcg_gen_movcond_tl(TCG_COND_NE, temp1, source2, zero, source1, mone);
+ tcg_gen_movcond_tl(TCG_COND_NE, temp2, source2, zero, source2, one);
+ tcg_gen_divu_tl(ret, temp1, temp2);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+}
+
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_ZERO, gen_divu);
}
+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp1, temp2, zero, one, mone, min;
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+ min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+ tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, source2, 0); /* temp2 = div0 */
+ tcg_gen_or_tl(temp2, temp2, temp1); /* temp2 = overflow | div0 */
+
+ /* if overflow or div by zero, set source2 to 1, else don't change */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, temp2, zero, source2, one);
+ tcg_gen_rem_tl(temp1, temp1, temp2);
+
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_NE, ret, source2, zero, temp1, source1);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+}
+
+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+{
+ TCGv temp2, zero, one;
+
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, source2, one);
+ tcg_gen_remu_tl(temp2, source1, temp2);
+
+ /* if div by zero, just return the original dividend */
+ tcg_gen_movcond_tl(TCG_COND_NE, ret, source2, zero, temp2, source1);
+
+ tcg_temp_free(temp2);
+}
+
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
--
2.25.1
next prev parent reply other threads:[~2021-08-17 21:20 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-17 21:17 [PATCH v2 00/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-17 21:17 ` [PATCH v2 01/21] " Richard Henderson
2021-08-18 7:23 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 02/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-18 9:20 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-17 22:15 ` Philippe Mathieu-Daudé
2021-08-18 9:27 ` Bin Meng
2021-08-19 6:20 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-18 10:58 ` Bin Meng
2021-08-19 1:16 ` Richard Henderson
2021-08-19 2:01 ` Richard Henderson
2021-08-19 6:25 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-19 2:42 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 06/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-19 2:43 ` Bin Meng
2021-08-19 6:28 ` Alistair Francis
2021-08-17 21:17 ` [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-19 3:03 ` Bin Meng
2021-08-19 6:29 ` Alistair Francis
2021-08-17 21:17 ` Richard Henderson [this message]
2021-08-17 22:19 ` [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-17 22:20 ` Philippe Mathieu-Daudé
2021-08-19 3:03 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-17 21:17 ` [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-19 6:13 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 12/21] target/riscv: Add gen_greviw Richard Henderson
2021-08-17 21:17 ` [PATCH v2 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-19 6:19 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-19 6:22 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-19 7:08 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:17 ` [PATCH v2 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-17 21:18 ` [PATCH v2 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-19 8:04 ` Bin Meng
2021-08-17 21:18 ` [PATCH v2 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-17 22:24 ` Philippe Mathieu-Daudé
2021-08-17 21:18 ` [PATCH v2 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
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