From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v3 52/66] target/alpha: Reorg fp memory operations
Date: Wed, 18 Aug 2021 09:19:06 -1000 [thread overview]
Message-ID: <20210818191920.390759-53-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org>
Pass in the context to each mini-helper, instead of an
incorrectly named "flags". Separate gen_load_fp and
gen_store_fp, away from the integer helpers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/translate.c | 83 +++++++++++++++++++++++++++-------------
1 file changed, 57 insertions(+), 26 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index de6c0a8439..607b6c3da7 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -267,30 +267,47 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
return gen_excp(ctx, EXCP_OPCDEC, 0);
}
-static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
+static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
- gen_helper_memory_to_f(t0, tmp32);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ gen_helper_memory_to_f(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
-static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
+static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv tmp = tcg_temp_new();
- tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ);
- gen_helper_memory_to_g(t0, tmp);
+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
+ gen_helper_memory_to_g(dest, tmp);
tcg_temp_free(tmp);
}
-static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
+static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
- gen_helper_memory_to_s(t0, tmp32);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ gen_helper_memory_to_s(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
+static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
+{
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
+}
+
+static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
+ void (*func)(DisasContext *, TCGv, TCGv))
+{
+ /* Loads to $f31 are prefetches, which we can treat as nops. */
+ if (likely(ra != 31)) {
+ TCGv addr = tcg_temp_new();
+ tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
+ func(ctx, cpu_fir[ra], addr);
+ tcg_temp_free(addr);
+ }
+}
+
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
@@ -338,30 +355,44 @@ static inline void gen_load_mem(DisasContext *ctx,
tcg_temp_free(tmp);
}
-static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
+static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- gen_helper_f_to_memory(tmp32, t0);
- tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
+ gen_helper_f_to_memory(tmp32, addr);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
tcg_temp_free_i32(tmp32);
}
-static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
+static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv tmp = tcg_temp_new();
- gen_helper_g_to_memory(tmp, t0);
- tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ);
+ gen_helper_g_to_memory(tmp, src);
+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
tcg_temp_free(tmp);
}
-static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
+static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- gen_helper_s_to_memory(tmp32, t0);
- tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
+ gen_helper_s_to_memory(tmp32, src);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
tcg_temp_free_i32(tmp32);
}
+static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
+{
+ tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
+}
+
+static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
+ void (*func)(DisasContext *, TCGv, TCGv))
+{
+ TCGv addr = tcg_temp_new();
+ tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
+ func(ctx, load_fpr(ctx, ra), addr);
+ tcg_temp_free(addr);
+}
+
static inline void gen_store_mem(DisasContext *ctx,
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
int flags),
@@ -2776,42 +2807,42 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x20:
/* LDF */
REQUIRE_FEN;
- gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_ldf);
break;
case 0x21:
/* LDG */
REQUIRE_FEN;
- gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_ldg);
break;
case 0x22:
/* LDS */
REQUIRE_FEN;
- gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_lds);
break;
case 0x23:
/* LDT */
REQUIRE_FEN;
- gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
+ gen_load_fp(ctx, ra, rb, disp16, gen_ldt);
break;
case 0x24:
/* STF */
REQUIRE_FEN;
- gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_stf);
break;
case 0x25:
/* STG */
REQUIRE_FEN;
- gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_stg);
break;
case 0x26:
/* STS */
REQUIRE_FEN;
- gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_sts);
break;
case 0x27:
/* STT */
REQUIRE_FEN;
- gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
+ gen_store_fp(ctx, ra, rb, disp16, gen_stt);
break;
case 0x28:
/* LDL */
--
2.25.1
next prev parent reply other threads:[~2021-08-18 19:44 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 19:18 [PATCH v3 00/66] Unaligned access for user-only Richard Henderson
2021-08-18 19:18 ` [PATCH v3 01/66] util: Suppress -Wstringop-overflow in qemu_thread_start Richard Henderson
2021-08-19 15:13 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 02/66] hw/core: Make do_unaligned_access noreturn Richard Henderson
2021-08-19 6:15 ` Alistair Francis
2021-08-18 19:18 ` [PATCH v3 03/66] hw/core: Make do_unaligned_access available to user-only Richard Henderson
2021-08-18 19:18 ` [PATCH v3 04/66] target/alpha: Implement do_unaligned_access for user-only Richard Henderson
2021-08-18 19:18 ` [PATCH v3 05/66] target/arm: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 06/66] target/hppa: " Richard Henderson
2021-08-19 15:32 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 07/66] target/microblaze: Do not set MO_ALIGN " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 08/66] target/mips: Implement do_unaligned_access " Richard Henderson
2021-08-19 15:34 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 09/66] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-08-19 15:39 ` Peter Maydell
2021-08-19 19:13 ` Richard Henderson
2021-08-18 19:18 ` [PATCH v3 10/66] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-08-19 15:41 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 11/66] target/ppc: Implement do_unaligned_access for user-only Richard Henderson
2021-08-19 15:44 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 12/66] target/riscv: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 13/66] target/s390x: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 14/66] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-08-18 19:18 ` [PATCH v3 15/66] target/sh4: Implement do_unaligned_access for user-only Richard Henderson
2021-08-19 15:46 ` Peter Maydell
2021-08-19 19:21 ` Richard Henderson
2021-08-18 19:18 ` [PATCH v3 16/66] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-08-18 19:18 ` [PATCH v3 17/66] target/sparc: Split out build_sfsr Richard Henderson
2021-08-18 19:18 ` [PATCH v3 18/66] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-08-18 19:18 ` [PATCH v3 19/66] target/sparc: Implement do_unaligned_access for user-only Richard Henderson
2021-08-18 19:18 ` [PATCH v3 20/66] target/xtensa: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 21/66] accel/tcg: Report unaligned atomics " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 22/66] accel/tcg: Drop signness in tracing in cputlb.c Richard Henderson
2021-08-18 21:14 ` Philippe Mathieu-Daudé
2021-08-18 19:18 ` [PATCH v3 23/66] tcg: Expand MO_SIZE to 3 bits Richard Henderson
2021-08-19 6:17 ` Alistair Francis
2021-08-18 19:18 ` [PATCH v3 24/66] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
2021-08-19 6:17 ` Alistair Francis
2021-08-18 19:18 ` [PATCH v3 25/66] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
2021-08-18 19:18 ` [PATCH v3 26/66] trace/mem: Pass MemOpIdx to trace_mem_get_info Richard Henderson
2021-08-19 15:49 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 27/66] accel/tcg: Pass MemOpIdx to atomic_trace_*_post Richard Henderson
2021-08-18 19:18 ` [PATCH v3 28/66] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
2021-08-30 21:42 ` Philippe Mathieu-Daudé
2021-08-18 19:18 ` [PATCH v3 29/66] trace: Split guest_mem_before Richard Henderson
2021-08-18 19:18 ` [PATCH v3 30/66] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
2021-08-18 19:18 ` [PATCH v3 31/66] target/i386: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 32/66] target/ppc: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 33/66] target/s390x: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 34/66] target/hexagon: Implement cpu_mmu_index Richard Henderson
2021-08-18 19:18 ` [PATCH v3 35/66] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
2021-08-19 15:57 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 36/66] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
2021-08-18 19:18 ` [PATCH v3 37/66] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
2021-08-18 19:18 ` [PATCH v3 38/66] target/mips: Use 8-byte memory ops " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 39/66] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
2021-08-18 19:18 ` [PATCH v3 40/66] target/sparc: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 41/66] target/arm: " Richard Henderson
2021-08-18 19:18 ` [PATCH v3 42/66] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
2021-08-18 19:18 ` [PATCH v3 43/66] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-08-19 15:58 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 44/66] tcg/i386: Support raising sigbus for user-only Richard Henderson
2021-08-19 16:02 ` Peter Maydell
2021-08-18 19:18 ` [PATCH v3 45/66] tests/tcg/multiarch: Add sigbus.c Richard Henderson
2021-08-19 16:04 ` Peter Maydell
2021-08-18 19:19 ` [PATCH v3 46/66] linux-user: Split out do_prctl and subroutines Richard Henderson
2021-08-19 16:06 ` Peter Maydell
2021-08-19 19:30 ` Richard Henderson
2021-08-18 19:19 ` [PATCH v3 47/66] linux-user: Disable more prctl subcodes Richard Henderson
2021-08-18 19:19 ` [PATCH v3 48/66] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass Richard Henderson
2021-08-18 21:17 ` Philippe Mathieu-Daudé
2021-08-18 19:19 ` [PATCH v3 49/66] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
2021-08-18 19:19 ` [PATCH v3 50/66] hw/core/cpu: Move cpu properties to cpu-sysemu.c Richard Henderson
2021-08-19 15:26 ` Peter Maydell
2021-08-19 16:52 ` Eduardo Habkost
2021-08-18 19:19 ` [PATCH v3 51/66] hw/core/cpu: Add prctl-unalign-sigbus property for user-only Richard Henderson
2021-08-18 19:19 ` Richard Henderson [this message]
2021-08-18 21:21 ` [PATCH v3 52/66] target/alpha: Reorg fp memory operations Philippe Mathieu-Daudé
2021-08-18 19:19 ` [PATCH v3 53/66] target/alpha: Reorg integer " Richard Henderson
2021-08-20 9:29 ` Peter Maydell
2021-08-18 19:19 ` [PATCH v3 54/66] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
2021-08-18 19:19 ` [PATCH v3 55/66] target/hppa: " Richard Henderson
2021-08-18 19:19 ` [PATCH v3 56/66] target/sh4: " Richard Henderson
2021-08-18 19:19 ` [PATCH v3 57/66] accel/tcg/user-exec: Convert DEBUG_SIGNAL to tracepoint Richard Henderson
2021-08-18 21:22 ` Philippe Mathieu-Daudé
2021-08-18 19:19 ` [PATCH v3 58/66] include/exec: Move cpu_signal_handler declaration Richard Henderson
2021-08-18 21:23 ` Philippe Mathieu-Daudé
2021-08-19 6:18 ` Alistair Francis
2021-08-18 19:19 ` [PATCH v3 59/66] accel/tcg: Handle SIGBUS in handle_cpu_signal Richard Henderson
2021-08-20 9:34 ` Peter Maydell
2021-08-22 7:48 ` Richard Henderson
2021-08-18 19:19 ` [PATCH v3 60/66] tcg/aarch64: Support raising sigbus for user-only Richard Henderson
2021-08-20 9:46 ` Peter Maydell
2021-08-18 19:19 ` [PATCH v3 61/66] tcg/ppc: " Richard Henderson
2021-08-20 10:11 ` Peter Maydell
2021-08-18 19:19 ` [PATCH v3 62/66] tcg/s390: " Richard Henderson
2021-08-20 10:12 ` Peter Maydell
2021-08-18 19:19 ` [PATCH v3 63/66] tcg/tci: " Richard Henderson
2021-08-20 10:14 ` Peter Maydell
2021-08-22 7:59 ` Richard Henderson
2021-08-22 12:32 ` Peter Maydell
2021-08-22 17:09 ` Richard Henderson
2021-08-18 19:19 ` [PATCH v3 64/66] tcg: Canonicalize alignment flags in MemOp Richard Henderson
2021-08-18 21:24 ` Philippe Mathieu-Daudé
2021-08-18 19:19 ` [PATCH v3 65/66] tcg/riscv: Support raising sigbus for user-only Richard Henderson
2021-08-18 19:19 ` [PATCH v3 66/66] tcg/riscv: Remove add with zero on user-only memory access Richard Henderson
2021-08-30 21:29 ` Philippe Mathieu-Daudé
2021-08-30 22:38 ` Alistair Francis
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