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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v3 16/16] tcg/mips: Try three insns with shift and add in tcg_out_movi
Date: Wed, 18 Aug 2021 10:19:31 -1000	[thread overview]
Message-ID: <20210818201931.393394-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org>

These sequences are inexpensive to test.  Maxing out at three insns
results in the same space as a load plus the constant pool entry.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/mips/tcg-target.c.inc | 44 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 27a23662c8..92f324de68 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -583,6 +583,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
                              tcg_target_long arg, TCGReg tbreg)
 {
     tcg_target_long tmp;
+    int sh, lo;
 
     if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
         arg = (int32_t)arg;
@@ -605,6 +606,49 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
         return;
     }
 
+    /*
+     * Load bitmasks with a right-shift.  This is good for things
+     * like 0x0fff_ffff_ffff_fff0: ADDUI r,0xff00 + DSRL r,r,4.
+     * or similarly using LUI.  For this to work, bit 31 must be set.
+     */
+    if (arg > 0 && (int32_t)arg < 0) {
+        sh = clz64(arg);
+        if (tcg_out_movi_one(s, ret, arg << sh)) {
+            tcg_out_dsrl(s, ret, ret, sh);
+            return;
+        }
+    }
+
+    /*
+     * Load slightly larger constants using left-shift.
+     * Limit this sequence to 3 insns to avoid too much expansion.
+     */
+    sh = ctz64(arg);
+    if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {
+        tcg_out_dsll(s, ret, ret, sh);
+        return;
+    }
+
+    /*
+     * Load slightly larger constants using left-shift and add/or.
+     * Prefer addi with a negative immediate when that would produce
+     * a larger shift.  For this to work, bits 15 and 16 must be set.
+     */
+    lo = arg & 0xffff;
+    if (lo) {
+        if ((arg & 0x18000) == 0x18000) {
+            lo = (int16_t)arg;
+        }
+        tmp = arg - lo;
+        sh = ctz64(tmp);
+        tmp >>= sh;
+        if (tcg_out_movi_one(s, ret, tmp)) {
+            tcg_out_dsll(s, ret, ret, sh);
+            tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
+            return;
+        }
+    }
+
     /* Otherwise, put 64-bit constants into the constant pool. */
     tcg_out_movi_pool(s, ret, arg, tbreg);
 }
-- 
2.25.1



  parent reply	other threads:[~2021-08-18 20:32 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-18 20:19 [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup Richard Henderson
2021-08-18 20:19 ` [PATCH v3 01/16] tcg/mips: Support unaligned access for user-only Richard Henderson
2021-08-18 20:19 ` [PATCH v3 02/16] tcg/mips: Support unaligned access for softmmu Richard Henderson
2021-08-21  6:39   ` Jiaxun Yang
2021-08-18 20:19 ` [PATCH v3 03/16] tcg/mips: Drop inline markers Richard Henderson
2021-08-18 21:03   ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 04/16] tcg/mips: Move TCG_AREG0 to S8 Richard Henderson
2021-08-18 22:10   ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 05/16] tcg/mips: Move TCG_GUEST_BASE_REG to S7 Richard Henderson
2021-08-18 22:11   ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 06/16] tcg/mips: Unify TCG_GUEST_BASE_REG tests Richard Henderson
2021-08-18 20:19 ` [PATCH v3 07/16] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Richard Henderson
2021-09-20 21:14   ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 08/16] tcg/mips: Unset TCG_TARGET_HAS_direct_jump Richard Henderson
2021-08-18 22:17   ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 09/16] tcg/mips: Drop special alignment for code_gen_buffer Richard Henderson
2021-08-18 22:19   ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 10/16] tcg/mips: Create and use TCG_REG_TB Richard Henderson
2021-08-18 20:19 ` [PATCH v3 11/16] tcg/mips: Split out tcg_out_movi_one Richard Henderson
2021-08-18 20:19 ` [PATCH v3 12/16] tcg/mips: Split out tcg_out_movi_two Richard Henderson
2021-08-18 20:19 ` [PATCH v3 13/16] tcg/mips: Use the constant pool for 64-bit constants Richard Henderson
2021-08-18 20:19 ` [PATCH v3 14/16] tcg/mips: Aggressively use the constant pool for n64 calls Richard Henderson
2021-08-18 20:19 ` [PATCH v3 15/16] tcg/mips: Try tb-relative addresses in tcg_out_movi Richard Henderson
2021-08-18 20:19 ` Richard Henderson [this message]
2021-08-18 22:07 ` [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup Philippe Mathieu-Daudé
2021-08-18 22:09   ` Philippe Mathieu-Daudé
2021-08-20  7:16     ` Huacai Chen

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