From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v3 03/16] tcg/mips: Drop inline markers
Date: Wed, 18 Aug 2021 10:19:18 -1000 [thread overview]
Message-ID: <20210818201931.393394-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org>
Let the compiler decide about inlining.
Remove tcg_out_ext8s and tcg_out_ext16s as unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 76 ++++++++++++++-------------------------
1 file changed, 27 insertions(+), 49 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 3d6a0ba39e..94f1bebdba 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -189,7 +189,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
#endif
-static inline bool is_p2m1(tcg_target_long val)
+static bool is_p2m1(tcg_target_long val)
{
return val && ((val + 1) & val) == 0;
}
@@ -373,8 +373,8 @@ typedef enum {
/*
* Type reg
*/
-static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
- TCGReg rd, TCGReg rs, TCGReg rt)
+static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
+ TCGReg rd, TCGReg rs, TCGReg rt)
{
int32_t inst;
@@ -388,8 +388,8 @@ static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
/*
* Type immediate
*/
-static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
- TCGReg rt, TCGReg rs, TCGArg imm)
+static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
+ TCGReg rt, TCGReg rs, TCGArg imm)
{
int32_t inst;
@@ -403,8 +403,8 @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
/*
* Type bitfield
*/
-static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
- TCGReg rs, int msb, int lsb)
+static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
+ TCGReg rs, int msb, int lsb)
{
int32_t inst;
@@ -416,8 +416,8 @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
tcg_out32(s, inst);
}
-static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
- MIPSInsn oph, TCGReg rt, TCGReg rs,
+static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
+ MIPSInsn oph, TCGReg rt, TCGReg rs,
int msb, int lsb)
{
if (lsb >= 32) {
@@ -434,8 +434,7 @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
/*
* Type branch
*/
-static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
- TCGReg rt, TCGReg rs)
+static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
{
tcg_out_opc_imm(s, opc, rt, rs, 0);
}
@@ -443,8 +442,8 @@ static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
/*
* Type sa
*/
-static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
- TCGReg rd, TCGReg rt, TCGArg sa)
+static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
+ TCGReg rd, TCGReg rt, TCGArg sa)
{
int32_t inst;
@@ -491,28 +490,27 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
return true;
}
-static inline void tcg_out_nop(TCGContext *s)
+static void tcg_out_nop(TCGContext *s)
{
tcg_out32(s, 0);
}
-static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
{
tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
}
-static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
{
tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
}
-static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
{
tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
}
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
/* Simple reg-reg move, optimising out the 'do nothing' case */
if (ret != arg) {
@@ -624,27 +622,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
}
}
-static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
- } else {
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
- tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
- }
-}
-
-static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
- } else {
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
- tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
- }
-}
-
-static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
@@ -668,8 +646,8 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
tcg_out_opc_imm(s, opc, data, addr, lo);
}
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
{
MIPSInsn opc = OPC_LD;
if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
@@ -678,8 +656,8 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
tcg_out_ldst(s, opc, arg, arg1, arg2);
}
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
{
MIPSInsn opc = OPC_SD;
if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
@@ -688,8 +666,8 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
tcg_out_ldst(s, opc, arg, arg1, arg2);
}
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
+static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
{
if (val == 0) {
tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
@@ -1960,9 +1938,9 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
}
}
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg args[TCG_MAX_OP_ARGS],
- const int const_args[TCG_MAX_OP_ARGS])
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
MIPSInsn i1, i2;
TCGArg a0, a1, a2;
--
2.25.1
next prev parent reply other threads:[~2021-08-18 20:24 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 20:19 [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup Richard Henderson
2021-08-18 20:19 ` [PATCH v3 01/16] tcg/mips: Support unaligned access for user-only Richard Henderson
2021-08-18 20:19 ` [PATCH v3 02/16] tcg/mips: Support unaligned access for softmmu Richard Henderson
2021-08-21 6:39 ` Jiaxun Yang
2021-08-18 20:19 ` Richard Henderson [this message]
2021-08-18 21:03 ` [PATCH v3 03/16] tcg/mips: Drop inline markers Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 04/16] tcg/mips: Move TCG_AREG0 to S8 Richard Henderson
2021-08-18 22:10 ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 05/16] tcg/mips: Move TCG_GUEST_BASE_REG to S7 Richard Henderson
2021-08-18 22:11 ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 06/16] tcg/mips: Unify TCG_GUEST_BASE_REG tests Richard Henderson
2021-08-18 20:19 ` [PATCH v3 07/16] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Richard Henderson
2021-09-20 21:14 ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 08/16] tcg/mips: Unset TCG_TARGET_HAS_direct_jump Richard Henderson
2021-08-18 22:17 ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 09/16] tcg/mips: Drop special alignment for code_gen_buffer Richard Henderson
2021-08-18 22:19 ` Philippe Mathieu-Daudé
2021-08-18 20:19 ` [PATCH v3 10/16] tcg/mips: Create and use TCG_REG_TB Richard Henderson
2021-08-18 20:19 ` [PATCH v3 11/16] tcg/mips: Split out tcg_out_movi_one Richard Henderson
2021-08-18 20:19 ` [PATCH v3 12/16] tcg/mips: Split out tcg_out_movi_two Richard Henderson
2021-08-18 20:19 ` [PATCH v3 13/16] tcg/mips: Use the constant pool for 64-bit constants Richard Henderson
2021-08-18 20:19 ` [PATCH v3 14/16] tcg/mips: Aggressively use the constant pool for n64 calls Richard Henderson
2021-08-18 20:19 ` [PATCH v3 15/16] tcg/mips: Try tb-relative addresses in tcg_out_movi Richard Henderson
2021-08-18 20:19 ` [PATCH v3 16/16] tcg/mips: Try three insns with shift and add " Richard Henderson
2021-08-18 22:07 ` [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup Philippe Mathieu-Daudé
2021-08-18 22:09 ` Philippe Mathieu-Daudé
2021-08-20 7:16 ` Huacai Chen
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