* [PATCH 1/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 2/9] hw/nvram: Introduce Xilinx eFuse QOM Tong Ho
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm; +Cc: edgar.iglesias, alistair, tong.ho, qemu-devel, peter.maydell
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
document.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
index 27f73500d9..84afac3734 100644
--- a/docs/system/arm/xlnx-versal-virt.rst
+++ b/docs/system/arm/xlnx-versal-virt.rst
@@ -32,6 +32,8 @@ Implemented devices:
- OCM (256KB of On Chip Memory)
- XRAM (4MB of on chip Accelerator RAM)
- DDR memory
+- BBRAM (36 bytes of Battery-backed RAM)
+- eFUSE (3072 bytes of one-time field-programmable bit array)
QEMU does not yet model any other devices, including the PL and the AI Engine.
@@ -175,3 +177,50 @@ Run the following at the U-Boot prompt:
fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000>
booti 30000000 - 20000000
+BBRAM File Backend
+""""""""""""""""""
+BBRAM can have an optional file backend, which must a seekable
+binary file with a size of 36 bytes or larger. A file with all
+binary 0s is a 'blank'.
+
+To add a file-backend for the BBRAM:
+
+.. code-block:: bash
+
+ -drive if=pflash,index=0,file=versal-bbram.bin,format=raw
+
+To use a different index value, N, from default of 0, add:
+
+.. code-block:: bash
+
+ -global xlnx,bbram-ctrl.drive-index=N
+
+eFUSE File Backend
+""""""""""""""""""
+eFUSE can have an optional file backend, which must a seekable
+binary file with a size of 3072 bytes or larger. A file with all
+binary 0s is a 'blank'.
+
+To add a file-backend for the eFUSE:
+
+.. code-block:: bash
+
+ -drive if=pflash,index=1,file=versal-efuse.bin,format=raw
+
+To use a different index value, N, from default of 1, add:
+
+.. code-block:: bash
+
+ -global xlnx,efuse.drive-index=N
+
+.. warning::
+ In actual physical Versal, BBRAM and eFUSE contain sensitive data.
+ The QEMU device models do **not** encrypt nor obfuscate any data
+ when holding them in models' memory or when writing them to their
+ file backends.
+
+ Thus, a file backend should be used with caution, and 'format=luks'
+ is highly recommended (albeit with usage complexity).
+
+ Better yet, do not use actual product data when running guest image
+ on this Xilinx Versal Virt board. |
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/9] hw/nvram: Introduce Xilinx eFuse QOM
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
2021-08-19 4:03 ` [PATCH 1/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 3/9] hw/nvram: Introduce Xilinx Versal eFuse device Tong Ho
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm
Cc: Edgar E . Iglesias, peter.maydell, Sai Pavan Boddu, alistair,
qemu-devel, tong.ho, edgar.iglesias
This introduces the QOM for Xilinx eFuse, an one-time
field-programmable storage bit array.
The actual mmio interface to the array varies by device
families and will be provided in different change-sets.
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/nvram/xlnx-efuse-crc.c | 118 ++++++++++++++++
hw/nvram/xlnx-efuse.c | 253 ++++++++++++++++++++++++++++++++++
include/hw/nvram/xlnx-efuse.h | 80 +++++++++++
3 files changed, 451 insertions(+)
create mode 100644 hw/nvram/xlnx-efuse-crc.c
create mode 100644 hw/nvram/xlnx-efuse.c
create mode 100644 include/hw/nvram/xlnx-efuse.h
diff --git a/hw/nvram/xlnx-efuse-crc.c b/hw/nvram/xlnx-efuse-crc.c
new file mode 100644
index 0000000000..bc12c39e00
--- /dev/null
+++ b/hw/nvram/xlnx-efuse-crc.c
@@ -0,0 +1,118 @@
+/*
+ * Xilinx eFuse/bbram CRC calculator
+ *
+ * Copyright (c) 2021 Xilinx Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/nvram/xlnx-efuse.h"
+
+static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data,
+ uint32_t addr)
+{
+ /* A table for 7-bit slicing */
+ static const uint32_t crc_tab[128] = {
+ 0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8,
+ 0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27,
+ 0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087,
+ 0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848,
+ 0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936,
+ 0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9,
+ 0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59,
+ 0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696,
+ 0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54,
+ 0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b,
+ 0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b,
+ 0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4,
+ 0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a,
+ 0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45,
+ 0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5,
+ 0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a,
+ 0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90,
+ 0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f,
+ 0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff,
+ 0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330,
+ 0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e,
+ 0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81,
+ 0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521,
+ 0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee,
+ 0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c,
+ 0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3,
+ 0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643,
+ 0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c,
+ 0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2,
+ 0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d,
+ 0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d,
+ 0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052
+ };
+
+ /*
+ * eFuse calculation is shown here:
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496
+ *
+ * Each u32 word is appended a 5-bit value, for a total of 37 bits; see:
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356
+ */
+ uint32_t crc = prev_crc;
+ const unsigned rshf = 7;
+ const uint32_t im = (1 << rshf) - 1;
+ const uint32_t rm = (1 << (32 - rshf)) - 1;
+ const uint32_t i2 = (1 << 2) - 1;
+ const uint32_t r2 = (1 << 30) - 1;
+
+ unsigned j;
+ uint32_t i, r;
+ uint64_t w;
+
+ w = (uint64_t)(addr) << 32;
+ w |= data;
+
+ /* Feed 35 bits, in 5 rounds, each a slice of 7 bits */
+ for (j = 0; j < 5; j++) {
+ r = rm & (crc >> rshf);
+ i = im & (crc ^ w);
+ crc = crc_tab[i] ^ r;
+
+ w >>= rshf;
+ }
+
+ /* Feed the remaining 2 bits */
+ r = r2 & (crc >> 2);
+ i = i2 & (crc ^ w);
+ crc = crc_tab[i << (rshf - 2)] ^ r;
+
+ return crc;
+}
+
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
+ unsigned zpads)
+{
+ uint32_t crc = 0;
+ unsigned index;
+
+ for (index = zpads; index; index--) {
+ crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt));
+ }
+
+ for (index = u32_cnt; index; index--) {
+ crc = xlnx_efuse_u37_crc(crc, data[index - 1], index);
+ }
+
+ return crc;
+}
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
new file mode 100644
index 0000000000..a51268874a
--- /dev/null
+++ b/hw/nvram/xlnx-efuse.c
@@ -0,0 +1,253 @@
+/*
+ * QEMU model of the EFUSE eFuse
+ *
+ * Copyright (c) 2015 Xilinx Inc.
+ *
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
+ * Partially autogenerated by xregqemu.py 2015-01-02.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nvram/xlnx-efuse.h"
+
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "sysemu/blockdev.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+
+#ifndef XLNX_EFUSE_ERR_DEBUG
+#define XLNX_EFUSE_ERR_DEBUG 0
+#endif
+
+#define XLNX_EFUSE(obj) \
+ OBJECT_CHECK(XLNXEFuse, (obj), TYPE_XLNX_EFUSE)
+
+#define TBIT0_OFFSET 28
+#define TBIT1_OFFSET 29
+#define TBIT2_OFFSET 30
+#define TBIT3_OFFSET 31
+#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET)
+#define TBITS_MASK (0x0FU << TBIT0_OFFSET)
+
+bool xlnx_efuse_get_bit(XLNXEFuse *s, unsigned int bit)
+{
+ bool b = s->fuse32[bit / 32] & (1 << (bit % 32));
+ return b;
+}
+
+static void efuse_sync_bdrv(XLNXEFuse *s, unsigned int bit)
+{
+ const int bswap_adj = (const_le32(0x1234) != 0x1234 ? 3 : 0);
+ unsigned int efuse_byte;
+
+ if (!s->blk || s->blk_ro) {
+ return; /* Silient on read-only backend to avoid message flood */
+ }
+
+ efuse_byte = bit / 8;
+
+ if (blk_pwrite(s->blk, efuse_byte,
+ ((uint8_t *) s->fuse32) + (efuse_byte ^ bswap_adj),
+ 1, 0) < 0) {
+ error_report("%s: write error in byte %" PRIu32 ".",
+ __func__, efuse_byte);
+ }
+}
+
+static int efuse_ro_bits_cmp(const void *a, const void *b)
+{
+ uint32_t i = *(const uint32_t *)a;
+ uint32_t j = *(const uint32_t *)b;
+
+ return (i > j) - (i < j);
+}
+
+static void efuse_ro_bits_sort(XLNXEFuse *s)
+{
+ uint32_t *ary = s->ro_bits;
+ const uint32_t cnt = s->ro_bits_cnt;
+
+ if (ary && cnt > 1) {
+ qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp);
+ }
+}
+
+static bool efuse_ro_bits_find(XLNXEFuse *s, uint32_t k)
+{
+ const uint32_t *ary = s->ro_bits;
+ const uint32_t cnt = s->ro_bits_cnt;
+
+ if (!ary || !cnt) {
+ return false;
+ }
+
+ return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL;
+}
+
+bool xlnx_efuse_set_bit(XLNXEFuse *s, unsigned int bit)
+{
+ if (efuse_ro_bits_find(s, bit)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: "
+ "Ignored setting of readonly efuse bit<%u,%u>!\n",
+ object_get_canonical_path(OBJECT(s)),
+ (bit / 32), (bit % 32));
+ return false;
+ }
+
+ s->fuse32[bit / 32] |= 1 << (bit % 32);
+ efuse_sync_bdrv(s, bit);
+ return true;
+}
+
+bool xlnx_efuse_k256_check(XLNXEFuse *s, uint32_t crc, unsigned start)
+{
+ uint32_t calc;
+
+ /* A key always occupies multiple of whole rows */
+ assert((start % 32) == 0);
+
+ calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0);
+ return calc == crc;
+}
+
+uint32_t xlnx_efuse_tbits_check(XLNXEFuse *s)
+{
+ int nr;
+ uint32_t check = 0;
+
+ for (nr = s->efuse_nr; nr-- > 0; ) {
+ int efuse_start_row_num = (s->efuse_size * nr) / 32;
+ uint32_t data = s->fuse32[efuse_start_row_num];
+
+ /*
+ * If the option is on, auto-init blank T-bits.
+ * (non-blank will still be reported as '0' in the check, e.g.,
+ * for error-injection tests)
+ */
+ if ((data & TBITS_MASK) == 0 && s->init_tbits) {
+ data |= TBITS_PATTERN;
+
+ s->fuse32[efuse_start_row_num] = data;
+ efuse_sync_bdrv(s, (efuse_start_row_num * 32 + TBIT0_OFFSET));
+ }
+
+ check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN);
+ }
+
+ return check;
+}
+
+static void efuse_realize(DeviceState *dev, Error **errp)
+{
+ XLNXEFuse *s = XLNX_EFUSE(dev);
+ BlockBackend *blk;
+ DriveInfo *dinfo;
+ unsigned int nr_bytes;
+ const char *prefix = object_get_canonical_path(OBJECT(dev));
+
+ if (s->drv_index < 0) {
+ /* Set legacy compatibility */
+ s->drv_index = s->efuse_size <= 2048 ? 3 : 1;
+ }
+
+ dinfo = drive_get_by_index(IF_PFLASH, s->drv_index);
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
+
+ nr_bytes = ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4);
+ s->fuse32 = g_malloc0(nr_bytes);
+ if (blk) {
+ qdev_prop_set_drive(dev, "drive", blk);
+
+ s->blk_ro = !blk_supports_write_perm(s->blk);
+ if (s->blk_ro) {
+ warn_report("%s: update not saved: backstore is read-only",
+ object_get_canonical_path(OBJECT(s)));
+ }
+ blk_set_perm(s->blk,
+ (BLK_PERM_CONSISTENT_READ
+ | (s->blk_ro ? 0 : BLK_PERM_WRITE)), BLK_PERM_ALL,
+ &error_abort);
+
+ if (blk_pread(s->blk, 0, (void *) s->fuse32, nr_bytes) < 0) {
+ error_setg(&error_abort, "%s: Unable to read-out contents."
+ "backing file too small? Expecting %" PRIu32" bytes",
+ prefix,
+ (unsigned int) (nr_bytes));
+ }
+ if (const_le32(0x1234) != 0x1234) {
+ /* Convert from little-endian backstore for each 32-bit row */
+ unsigned int nr_u32;
+
+ for (nr_u32 = 0; nr_u32 < (nr_bytes / 4); nr_u32++) {
+ s->fuse32[nr_u32] = le32_to_cpu(s->fuse32[nr_u32]);
+ }
+ }
+ }
+
+ /* Sort readonly-list for bsearch lookup */
+ efuse_ro_bits_sort(s);
+}
+
+static Property efuse_properties[] = {
+ DEFINE_PROP_UINT8("efuse-nr", XLNXEFuse, efuse_nr, 3),
+ DEFINE_PROP_UINT32("efuse-size", XLNXEFuse, efuse_size, 64 * 32),
+ DEFINE_PROP_INT32("drive-index", XLNXEFuse, drv_index, -1),
+ DEFINE_PROP_DRIVE("drive", XLNXEFuse, blk),
+ DEFINE_PROP_BOOL("init-factory-tbits", XLNXEFuse, init_tbits, true),
+ DEFINE_PROP_ARRAY("read-only", XLNXEFuse, ro_bits_cnt, ro_bits,
+ qdev_prop_uint32, uint32_t),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static const VMStateDescription vmstate_efuse = {
+ .name = TYPE_XLNX_EFUSE,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void efuse_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = efuse_realize;
+ dc->vmsd = &vmstate_efuse;
+ device_class_set_props(dc, efuse_properties);
+}
+
+static const TypeInfo efuse_info = {
+ .name = TYPE_XLNX_EFUSE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(XLNXEFuse),
+ .class_init = efuse_class_init,
+};
+
+static void efuse_register_types(void)
+{
+ type_register_static(&efuse_info);
+}
+type_init(efuse_register_types)
diff --git a/include/hw/nvram/xlnx-efuse.h b/include/hw/nvram/xlnx-efuse.h
new file mode 100644
index 0000000000..0aee3f84d7
--- /dev/null
+++ b/include/hw/nvram/xlnx-efuse.h
@@ -0,0 +1,80 @@
+/*
+ * QEMU model of the Xilinx eFuse core
+ *
+ * Copyright (c) 2015 Xilinx Inc.
+ *
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef XLNX_EFUSE_H
+#define XLNX_EFUSE_H
+
+#include "qemu/osdep.h"
+#include "sysemu/block-backend.h"
+#include "hw/qdev-core.h"
+
+#define TYPE_XLNX_EFUSE "xlnx,efuse"
+
+typedef struct XLNXEFuseLkSpec {
+ uint16_t row;
+ uint16_t lk_bit;
+} XLNXEFuseLkSpec;
+
+typedef struct XLNXEFuse {
+ DeviceState parent_obj;
+ BlockBackend *blk;
+ bool blk_ro;
+ uint32_t *fuse32;
+
+ DeviceState *dev;
+
+ bool init_tbits;
+ int drv_index;
+
+ uint8_t efuse_nr;
+ uint32_t efuse_size;
+
+ uint32_t *ro_bits;
+ uint32_t ro_bits_cnt;
+} XLNXEFuse;
+
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
+ unsigned zpads);
+
+bool xlnx_efuse_get_bit(XLNXEFuse *s, unsigned int bit);
+bool xlnx_efuse_set_bit(XLNXEFuse *s, unsigned int bit);
+bool xlnx_efuse_k256_check(XLNXEFuse *s, uint32_t crc, unsigned start);
+uint32_t xlnx_efuse_tbits_check(XLNXEFuse *s);
+
+/* Return whole row containing the given bit address */
+static inline uint32_t xlnx_efuse_get_row(XLNXEFuse *s, unsigned int bit)
+{
+ if (!(s->fuse32)) {
+ return 0;
+ } else {
+ unsigned int row_idx = bit / 32;
+
+ assert(row_idx < (s->efuse_size * s->efuse_nr / 32));
+ return s->fuse32[row_idx];
+ }
+}
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 3/9] hw/nvram: Introduce Xilinx Versal eFuse device
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
2021-08-19 4:03 ` [PATCH 1/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage Tong Ho
2021-08-19 4:03 ` [PATCH 2/9] hw/nvram: Introduce Xilinx eFuse QOM Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 4/9] hw/nvram: Introduce Xilinx ZynqMP " Tong Ho
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm
Cc: Edgar E . Iglesias, peter.maydell, Sai Pavan Boddu, alistair,
qemu-devel, tong.ho, edgar.iglesias
This implements the Xilinx Versal eFuse, an one-time
field-programmable non-volatile storage device. There is
only one such device in the Xilinx Versal product family.
The command argument:
-drive if=pflash,index=N,...
Can be used to optionally connect the storage array to a
backend storage, such that field-programmed values in one
invocation can be made available to next invocation.
The backend storage must be a seekable binary file, and
its size must be 3072 bytes or larger. A file with all
binary 0's is a 'blank'.
The drive 'index' value N has a default value of 1, but
can be changed using command argument:
-global xlnx,efuse.drive-index=N
This device has two separate mmio interfaces, a controller
and a flatten readback.
The controller provides interfaces for field-programming,
configuration, control, and status.
The flatten readback is a cache to provide a byte-accessible
read-only interface to efficiently read efuse array.
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/nvram/Kconfig | 8 +
hw/nvram/meson.build | 8 +
hw/nvram/xlnx-versal-efuse-cache.c | 141 +++++
hw/nvram/xlnx-versal-efuse-ctrl.c | 786 +++++++++++++++++++++++++++
include/hw/nvram/xlnx-versal-efuse.h | 62 +++
5 files changed, 1005 insertions(+)
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
index e872fcb194..e96749ced3 100644
--- a/hw/nvram/Kconfig
+++ b/hw/nvram/Kconfig
@@ -15,3 +15,11 @@ config NMC93XX_EEPROM
config CHRP_NVRAM
bool
+
+config XLNX_EFUSE
+ bool
+
+config XLNX_EFUSE_VERSAL
+ bool
+ default y if XLNX_VERSAL
+ select XLNX_EFUSE
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index fd2951a860..a432665158 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -9,5 +9,13 @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
+ 'xlnx-versal-efuse-cache.c',
+ 'xlnx-versal-efuse-ctrl.c'))
+if 'CONFIG_XLNX_BBRAM' in config_all or \
+ 'CONFIG_XLNX_EFUSE' in config_all
+ softmmu_ss.add(files('xlnx-efuse-crc.c'))
+endif
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c
new file mode 100644
index 0000000000..8b4eca7a39
--- /dev/null
+++ b/hw/nvram/xlnx-versal-efuse-cache.c
@@ -0,0 +1,141 @@
+/*
+ * QEMU model of the EFuse_Cache
+ *
+ * Copyright (c) 2017 Xilinx Inc.
+ *
+ * Partially generated by xregqemu.py 2017-06-05.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nvram/xlnx-versal-efuse.h"
+
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+
+#ifndef XILINX_EFUSE_CACHE_ERR_DEBUG
+#define XILINX_EFUSE_CACHE_ERR_DEBUG 0
+#endif
+
+#define XILINX_EFUSE_CACHE(obj) \
+ OBJECT_CHECK(XlnxVersalEFuseCache, (obj), TYPE_XLNX_VERSAL_EFUSE_CACHE)
+
+#define DPRINT(...) \
+ if (XILINX_EFUSE_CACHE_ERR_DEBUG) { \
+ qemu_log(__VA_ARGS__); \
+ }
+
+#define DPRINT_GE(args, ...) \
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: " args, __func__, ## __VA_ARGS__);
+
+#define MR_SIZE 0xC00
+
+static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size)
+{
+ XlnxVersalEFuseCache *s = XILINX_EFUSE_CACHE(opaque);
+ unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32);
+ unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32);
+
+ uint64_t ret;
+
+ assert(w0 == w1 || (w0 + 32) == w1);
+
+ ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL);
+ if (w0 < w1) {
+ ret <<= 32;
+ ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL);
+ }
+
+ /* If 'addr' unaligned, the guest is always assumed to be little-endian. */
+ addr &= 3;
+ if (addr) {
+ ret >>= 8 * addr;
+ }
+
+ return ret;
+}
+
+static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ /* No Register Writes allowed */
+ DPRINT_GE("Invalid write to efuse cache registers");
+}
+
+static const MemoryRegionOps efuse_cache_ops = {
+ .read = efuse_cache_read,
+ .write = efuse_cache_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void efuse_cache_init(Object *obj)
+{
+ XlnxVersalEFuseCache *s = XILINX_EFUSE_CACHE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s,
+ TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_efuse_cache = {
+ .name = TYPE_XLNX_VERSAL_EFUSE_CACHE,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property efuse_cache_props[] = {
+ DEFINE_PROP_LINK("efuse",
+ XlnxVersalEFuseCache, efuse,
+ TYPE_XLNX_EFUSE, XLNXEFuse *),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void efuse_cache_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_efuse_cache;
+ device_class_set_props(dc, efuse_cache_props);
+}
+
+static const TypeInfo efuse_cache_info = {
+ .name = TYPE_XLNX_VERSAL_EFUSE_CACHE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalEFuseCache),
+ .class_init = efuse_cache_class_init,
+ .instance_init = efuse_cache_init,
+};
+
+static void efuse_cache_register_types(void)
+{
+ type_register_static(&efuse_cache_info);
+}
+
+type_init(efuse_cache_register_types)
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
new file mode 100644
index 0000000000..0173a18a99
--- /dev/null
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
@@ -0,0 +1,786 @@
+/*
+ * QEMU model of the Versal eFuse controller
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Autogenerated by xregqemu.py 2020-01-16.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nvram/xlnx-versal-efuse.h"
+
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+
+#ifndef XILINX_EFUSE_CTRL_ERR_DEBUG
+#define XILINX_EFUSE_CTRL_ERR_DEBUG 0
+#endif
+
+#define XILINX_EFUSE_CTRL(obj) \
+ OBJECT_CHECK(XlnxVersalEFuseCtrl, (obj), TYPE_XLNX_VERSAL_EFUSE_CTRL)
+
+REG32(WR_LOCK, 0x0)
+ FIELD(WR_LOCK, LOCK, 0, 16)
+REG32(CFG, 0x4)
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
+ FIELD(CFG, MARGIN_RD, 2, 1)
+ FIELD(CFG, PGM_EN, 1, 1)
+REG32(STATUS, 0x8)
+ FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1)
+ FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1)
+ FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1)
+ FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
+ FIELD(STATUS, CACHE_DONE, 5, 1)
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
+ FIELD(STATUS, EFUSE_2_TBIT, 2, 1)
+ FIELD(STATUS, EFUSE_1_TBIT, 1, 1)
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
+REG32(EFUSE_PGM_ADDR, 0xc)
+ FIELD(EFUSE_PGM_ADDR, PAGE, 13, 4)
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 8)
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
+REG32(EFUSE_RD_ADDR, 0x10)
+ FIELD(EFUSE_RD_ADDR, PAGE, 13, 4)
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 8)
+REG32(EFUSE_RD_DATA, 0x14)
+REG32(TPGM, 0x18)
+ FIELD(TPGM, VALUE, 0, 16)
+REG32(TRD, 0x1c)
+ FIELD(TRD, VALUE, 0, 8)
+REG32(TSU_H_PS, 0x20)
+ FIELD(TSU_H_PS, VALUE, 0, 8)
+REG32(TSU_H_PS_CS, 0x24)
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
+REG32(TRDM, 0x28)
+ FIELD(TRDM, VALUE, 0, 8)
+REG32(TSU_H_CS, 0x2c)
+ FIELD(TSU_H_CS, VALUE, 0, 8)
+REG32(EFUSE_ISR, 0x30)
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_ISR, CACHE_PARITY_E2, 14, 1)
+ FIELD(EFUSE_ISR, CACHE_PARITY_E1, 13, 1)
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0S, 12, 1)
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0R, 11, 1)
+ FIELD(EFUSE_ISR, CACHE_APB_SLVERR, 10, 1)
+ FIELD(EFUSE_ISR, CACHE_REQ_ERROR, 9, 1)
+ FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1)
+ FIELD(EFUSE_ISR, READ_ON_CACHE_LD, 7, 1)
+ FIELD(EFUSE_ISR, CACHE_FSM_ERROR, 6, 1)
+ FIELD(EFUSE_ISR, MAIN_FSM_ERROR, 5, 1)
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
+REG32(EFUSE_IMR, 0x34)
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_IMR, CACHE_PARITY_E2, 14, 1)
+ FIELD(EFUSE_IMR, CACHE_PARITY_E1, 13, 1)
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0S, 12, 1)
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0R, 11, 1)
+ FIELD(EFUSE_IMR, CACHE_APB_SLVERR, 10, 1)
+ FIELD(EFUSE_IMR, CACHE_REQ_ERROR, 9, 1)
+ FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1)
+ FIELD(EFUSE_IMR, READ_ON_CACHE_LD, 7, 1)
+ FIELD(EFUSE_IMR, CACHE_FSM_ERROR, 6, 1)
+ FIELD(EFUSE_IMR, MAIN_FSM_ERROR, 5, 1)
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
+REG32(EFUSE_IER, 0x38)
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_IER, CACHE_PARITY_E2, 14, 1)
+ FIELD(EFUSE_IER, CACHE_PARITY_E1, 13, 1)
+ FIELD(EFUSE_IER, CACHE_PARITY_E0S, 12, 1)
+ FIELD(EFUSE_IER, CACHE_PARITY_E0R, 11, 1)
+ FIELD(EFUSE_IER, CACHE_APB_SLVERR, 10, 1)
+ FIELD(EFUSE_IER, CACHE_REQ_ERROR, 9, 1)
+ FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1)
+ FIELD(EFUSE_IER, READ_ON_CACHE_LD, 7, 1)
+ FIELD(EFUSE_IER, CACHE_FSM_ERROR, 6, 1)
+ FIELD(EFUSE_IER, MAIN_FSM_ERROR, 5, 1)
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
+REG32(EFUSE_IDR, 0x3c)
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_IDR, CACHE_PARITY_E2, 14, 1)
+ FIELD(EFUSE_IDR, CACHE_PARITY_E1, 13, 1)
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0S, 12, 1)
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0R, 11, 1)
+ FIELD(EFUSE_IDR, CACHE_APB_SLVERR, 10, 1)
+ FIELD(EFUSE_IDR, CACHE_REQ_ERROR, 9, 1)
+ FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1)
+ FIELD(EFUSE_IDR, READ_ON_CACHE_LD, 7, 1)
+ FIELD(EFUSE_IDR, CACHE_FSM_ERROR, 6, 1)
+ FIELD(EFUSE_IDR, MAIN_FSM_ERROR, 5, 1)
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
+REG32(EFUSE_CACHE_LOAD, 0x40)
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
+REG32(EFUSE_PGM_LOCK, 0x44)
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
+REG32(EFUSE_AES_CRC, 0x48)
+REG32(EFUSE_AES_USR_KEY0_CRC, 0x4c)
+REG32(EFUSE_AES_USR_KEY1_CRC, 0x50)
+REG32(EFUSE_PD, 0x54)
+REG32(EFUSE_ANLG_OSC_SW_1LP, 0x60)
+REG32(EFUSE_TEST_CTRL, 0x100)
+
+#define R_MAX (R_EFUSE_TEST_CTRL + 1)
+
+#define R_WR_LOCK_UNLOCK_PASSCODE (0xDF0D)
+
+/*
+ * eFuse layout references:
+ * UG????, p.???, Table ???
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse_hw.h
+ */
+#define BIT_POS_OF(A_) \
+ ((uint32_t)((A_) & (R_EFUSE_PGM_ADDR_ROW_MASK | \
+ R_EFUSE_PGM_ADDR_COLUMN_MASK)))
+
+#define BIT_POS(R_, C_) \
+ ((uint32_t)((R_EFUSE_PGM_ADDR_ROW_MASK \
+ & ((R_) << R_EFUSE_PGM_ADDR_ROW_SHIFT)) \
+ | \
+ (R_EFUSE_PGM_ADDR_COLUMN_MASK \
+ & ((C_) << R_EFUSE_PGM_ADDR_COLUMN_SHIFT))))
+
+#define EFUSE_TBIT_POS(A_) (BIT_POS_OF(A_) >= BIT_POS(0, 28))
+
+#define EFUSE_ANCHOR_ROW (0)
+#define EFUSE_ANCHOR_3_COL (27)
+#define EFUSE_ANCHOR_1_COL (1)
+
+#define EFUSE_AES_KEY_START BIT_POS(12, 0)
+#define EFUSE_AES_KEY_END BIT_POS(19, 31)
+#define EFUSE_USER_KEY_0_START BIT_POS(20, 0)
+#define EFUSE_USER_KEY_0_END BIT_POS(27, 31)
+#define EFUSE_USER_KEY_1_START BIT_POS(28, 0)
+#define EFUSE_USER_KEY_1_END BIT_POS(35, 31)
+
+#define EFUSE_RD_BLOCKED_START EFUSE_AES_KEY_START
+#define EFUSE_RD_BLOCKED_END EFUSE_USER_KEY_1_END
+
+#define EFUSE_GLITCH_DET_WR_LK BIT_POS(4, 31)
+#define EFUSE_PPK0_WR_LK BIT_POS(43, 6)
+#define EFUSE_PPK1_WR_LK BIT_POS(43, 7)
+#define EFUSE_PPK2_WR_LK BIT_POS(43, 8)
+#define EFUSE_AES_WR_LK BIT_POS(43, 11)
+#define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13)
+#define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15)
+#define EFUSE_PUF_SYN_LK BIT_POS(43, 16)
+#define EFUSE_DNA_WR_LK BIT_POS(43, 27)
+#define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28)
+
+#define EFUSE_PGM_LOCKED_START BIT_POS(44, 0)
+#define EFUSE_PGM_LOCKED_END BIT_POS(51, 31)
+
+#define EFUSE_PUF_PAGE (2)
+#define EFUSE_PUF_SYN_START BIT_POS(129, 0)
+#define EFUSE_PUF_SYN_END BIT_POS(255, 27)
+
+#define EFUSE_KEY_CRC_LK_ROW (43)
+#define EFUSE_AES_KEY_CRC_LK_MASK ((1U << 9) | (1U << 10))
+#define EFUSE_USER_KEY_0_CRC_LK_MASK (1U << 12)
+#define EFUSE_USER_KEY_1_CRC_LK_MASK (1U << 14)
+
+/*
+ * A handy macro to return value of an array element,
+ * or a specific default if given index is out of bound.
+ */
+#define ARRAY_GET(A_, I_, D_) \
+ ((unsigned int)(I_) < ARRAY_SIZE(A_) ? (A_)[I_] : (D_))
+
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs));
+
+static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s)
+{
+ bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR];
+ qemu_set_irq(s->irq_efuse_imr, pending);
+}
+
+static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+ efuse_imr_update_irq(s);
+}
+
+static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_EFUSE_IMR] &= ~val;
+ efuse_imr_update_irq(s);
+ return 0;
+}
+
+static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_EFUSE_IMR] |= val;
+ efuse_imr_update_irq(s);
+ return 0;
+}
+
+static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s)
+{
+ uint32_t check = xlnx_efuse_tbits_check(s->efuse);
+ uint32_t val = s->regs[R_STATUS];
+
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
+ val = FIELD_DP32(val, STATUS, EFUSE_1_TBIT, !!(check & (1 << 1)));
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 2)));
+
+ s->regs[R_STATUS] = val;
+}
+
+static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s)
+{
+ unsigned page;
+
+ if (!s->efuse || !s->efuse->init_tbits) {
+ return;
+ }
+
+ for (page = 0; page < s->efuse->efuse_nr; page++) {
+ uint32_t row = 0, bit;
+
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, PAGE, page);
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, ROW, EFUSE_ANCHOR_ROW);
+
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL);
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
+ xlnx_efuse_set_bit(s->efuse, bit);
+ }
+
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL);
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
+ xlnx_efuse_set_bit(s->efuse, bit);
+ }
+ }
+}
+
+static void efuse_key_crc_check(RegisterInfo *reg, uint32_t crc,
+ uint32_t pass_mask, uint32_t done_mask,
+ unsigned first, uint32_t lk_mask)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+ uint32_t r, lk_bits;
+
+ /*
+ * To start, assume both DONE and PASS, and clear PASS by xor
+ * if CRC-check fails or CRC-check disabled by lock fuse.
+ */
+ r = s->regs[R_STATUS] | done_mask | pass_mask;
+
+ lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask;
+ if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) {
+ pass_mask = 0;
+ }
+
+ s->regs[R_STATUS] = r ^ pass_mask;
+}
+
+static void efuse_data_sync(XlnxVersalEFuseCtrl *s)
+{
+ efuse_status_tbits_sync(s);
+}
+
+static int efuse_lk_spec_cmp(const void *a, const void *b)
+{
+ uint16_t r1 = ((const XLNXEFuseLkSpec *)a)->row;
+ uint16_t r2 = ((const XLNXEFuseLkSpec *)b)->row;
+
+ return (r1 > r2) - (r1 < r2);
+}
+
+static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s)
+{
+ XLNXEFuseLkSpec *ary = s->extra_pg0_lock.spec;
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
+ const uint32_t sz = sizeof(ary[0]);
+ const uint32_t cnt = n8 / sz;
+
+ if (!ary || !n8) {
+ return;
+ }
+
+ if ((n8 % sz) != 0) {
+ error_setg(&error_abort,
+ "%s: property 'pg0-lock' item-count not multiple of %u",
+ object_get_canonical_path(OBJECT(s)), sz);
+ }
+
+ qsort(ary, cnt, sz, efuse_lk_spec_cmp);
+}
+
+static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row)
+{
+ const XLNXEFuseLkSpec *ary = s->extra_pg0_lock.spec;
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
+ const uint32_t sz = sizeof(ary[0]);
+ const uint32_t cnt = n8 / sz;
+ const XLNXEFuseLkSpec *item = NULL;
+
+ if (ary && cnt) {
+ XLNXEFuseLkSpec k = { .row = row, };
+
+ item = bsearch(&k, ary, cnt, sz, efuse_lk_spec_cmp);
+ }
+
+ return item ? item->lk_bit : 0;
+}
+
+static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit)
+{
+ /* Hard-coded locks */
+ static const uint16_t pg0_hard_lock[] = {
+ [4] = EFUSE_GLITCH_DET_WR_LK,
+ [37] = EFUSE_BOOT_ENV_WR_LK,
+
+ [8 ... 11] = EFUSE_DNA_WR_LK,
+ [12 ... 19] = EFUSE_AES_WR_LK,
+ [20 ... 27] = EFUSE_USER_KEY_0_WR_LK,
+ [28 ... 35] = EFUSE_USER_KEY_1_WR_LK,
+ [64 ... 71] = EFUSE_PPK0_WR_LK,
+ [72 ... 79] = EFUSE_PPK1_WR_LK,
+ [80 ... 87] = EFUSE_PPK2_WR_LK,
+ };
+
+ uint32_t row = FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW);
+ uint32_t lk_bit = ARRAY_GET(pg0_hard_lock, row, 0);
+
+ return lk_bit ? lk_bit : efuse_lk_spec_find(s, row);
+}
+
+static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit)
+{
+
+ unsigned int lock = 1;
+
+ /* Global lock */
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
+ goto ret_lock;
+ }
+
+ /* Row lock */
+ switch (FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE)) {
+ case 0:
+ if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) &&
+ bit >= EFUSE_PGM_LOCKED_START && bit <= EFUSE_PGM_LOCKED_END) {
+ goto ret_lock;
+ }
+
+ lock = efuse_bit_locked(s, bit);
+ break;
+ case EFUSE_PUF_PAGE:
+ if (bit < EFUSE_PUF_SYN_START || bit > EFUSE_PUF_SYN_END) {
+ lock = 0;
+ goto ret_lock;
+ }
+
+ lock = EFUSE_PUF_SYN_LK;
+ break;
+ default:
+ lock = 0;
+ goto ret_lock;
+ }
+
+ /* Row lock by an efuse bit */
+ if (lock) {
+ lock = xlnx_efuse_get_bit(s->efuse, lock);
+ }
+
+ ret_lock:
+ return lock != 0;
+}
+
+static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+ unsigned bit = val64;
+ bool ok = false;
+
+ /* Always zero out PGM_ADDR because it is write-only */
+ s->regs[R_EFUSE_PGM_ADDR] = 0;
+
+ /*
+ * Indicate error if bit is write-protected (or read-only
+ * as guarded by efuse_set_bit()).
+ *
+ * Keep it simple by not modeling program timing.
+ *
+ * Note: model must NEVER clear the PGM_ERROR bit; it is
+ * up to guest to do so (or by reset).
+ */
+ if (efuse_pgm_locked(s, bit)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Denied setting of efuse<%u, %u, %u>\n",
+ object_get_canonical_path(OBJECT(s)),
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE),
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW),
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN));
+ } else if (xlnx_efuse_set_bit(s->efuse, bit)) {
+ ok = true;
+ if (EFUSE_TBIT_POS(bit)) {
+ efuse_status_tbits_sync(s);
+ }
+ }
+
+ if (!ok) {
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
+ }
+
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
+ efuse_imr_update_irq(s);
+}
+
+static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+ unsigned bit = val64;
+ bool denied;
+
+ /* Always zero out RD_ADDR because it is write-only */
+ s->regs[R_EFUSE_RD_ADDR] = 0;
+
+ /*
+ * Indicate error if row is read-blocked.
+ *
+ * Note: model must NEVER clear the RD_ERROR bit; it is
+ * up to guest to do so (or by reset).
+ */
+ s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse,
+ bit, &denied);
+ if (denied) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Denied reading of efuse<%u, %u>\n",
+ object_get_canonical_path(OBJECT(s)),
+ FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE),
+ FIELD_EX32(bit, EFUSE_RD_ADDR, ROW));
+
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
+ }
+
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
+ efuse_imr_update_irq(s);
+ return;
+}
+
+static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+
+ if (val64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
+ efuse_data_sync(s);
+
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
+ efuse_imr_update_irq(s);
+ }
+
+ return 0;
+}
+
+static uint64_t efuse_pgm_lock_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(reg->opaque);
+
+ /* Ignore all other bits */
+ val64 = FIELD_EX32(val64, EFUSE_PGM_LOCK, SPK_ID_LOCK);
+
+ /* Once the bit is written 1, only reset will clear it to 0 */
+ val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK);
+
+ return val64;
+}
+
+static void efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
+{
+ efuse_key_crc_check(reg, val64,
+ R_STATUS_AES_CRC_PASS_MASK,
+ R_STATUS_AES_CRC_DONE_MASK,
+ EFUSE_AES_KEY_START,
+ EFUSE_AES_KEY_CRC_LK_MASK);
+}
+
+static void efuse_aes_u0_crc_postw(RegisterInfo *reg, uint64_t val64)
+{
+ efuse_key_crc_check(reg, val64,
+ R_STATUS_AES_USER_KEY_0_CRC_PASS_MASK,
+ R_STATUS_AES_USER_KEY_0_CRC_DONE_MASK,
+ EFUSE_USER_KEY_0_START,
+ EFUSE_USER_KEY_0_CRC_LK_MASK);
+}
+
+static void efuse_aes_u1_crc_postw(RegisterInfo *reg, uint64_t val64)
+{
+ efuse_key_crc_check(reg, val64,
+ R_STATUS_AES_USER_KEY_1_CRC_PASS_MASK,
+ R_STATUS_AES_USER_KEY_1_CRC_DONE_MASK,
+ EFUSE_USER_KEY_1_START,
+ EFUSE_USER_KEY_1_CRC_LK_MASK);
+}
+
+static uint64_t efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
+{
+ return val != R_WR_LOCK_UNLOCK_PASSCODE;
+}
+
+static const RegisterAccessInfo efuse_ctrl_regs_info[] = {
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
+ .reset = 0x1,
+ .pre_write = efuse_wr_lock_prew,
+ },{ .name = "CFG", .addr = A_CFG,
+ .rsvd = 0x9,
+ },{ .name = "STATUS", .addr = A_STATUS,
+ .rsvd = 0x8,
+ .ro = 0xfff,
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
+ .post_write = efuse_pgm_addr_postw,
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
+ .rsvd = 0x1f,
+ .post_write = efuse_rd_addr_postw,
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
+ .ro = 0xffffffff,
+ },{ .name = "TPGM", .addr = A_TPGM,
+ },{ .name = "TRD", .addr = A_TRD,
+ .reset = 0x19,
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
+ .reset = 0xff,
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
+ .reset = 0x11,
+ },{ .name = "TRDM", .addr = A_TRDM,
+ .reset = 0x3a,
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
+ .reset = 0x16,
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
+ .rsvd = 0x7fff8000,
+ .w1c = 0x80007fff,
+ .post_write = efuse_isr_postw,
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
+ .reset = 0x80007fff,
+ .rsvd = 0x7fff8000,
+ .ro = 0xffffffff,
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
+ .rsvd = 0x7fff8000,
+ .pre_write = efuse_ier_prew,
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
+ .rsvd = 0x7fff8000,
+ .pre_write = efuse_idr_prew,
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
+ .pre_write = efuse_cache_load_prew,
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
+ .pre_write = efuse_pgm_lock_prew,
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
+ .post_write = efuse_aes_crc_postw,
+ },{ .name = "EFUSE_AES_USR_KEY0_CRC", .addr = A_EFUSE_AES_USR_KEY0_CRC,
+ .post_write = efuse_aes_u0_crc_postw,
+ },{ .name = "EFUSE_AES_USR_KEY1_CRC", .addr = A_EFUSE_AES_USR_KEY1_CRC,
+ .post_write = efuse_aes_u1_crc_postw,
+ },{ .name = "EFUSE_PD", .addr = A_EFUSE_PD,
+ .ro = 0xfffffffe,
+ },{ .name = "EFUSE_ANLG_OSC_SW_1LP", .addr = A_EFUSE_ANLG_OSC_SW_1LP,
+ },{ .name = "EFUSE_TEST_CTRL", .addr = A_EFUSE_TEST_CTRL,
+ .reset = 0x8,
+ }
+};
+
+static void efuse_ctrl_reg_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ RegisterInfoArray *reg_array = opaque;
+ XlnxVersalEFuseCtrl *s;
+ Object *dev;
+
+ assert(reg_array != NULL);
+
+ dev = reg_array->mem.owner;
+ assert(dev);
+
+ s = XILINX_EFUSE_CTRL(dev);
+
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
+ object_get_canonical_path(OBJECT(s)), (long)addr);
+ } else {
+ register_write_memory(opaque, addr, data, size);
+ }
+}
+
+static void efuse_ctrl_register_reset(RegisterInfo *reg)
+{
+ if (!reg->data || !reg->access) {
+ return;
+ }
+
+ /* Reset must not trigger some registers' writers */
+ switch (reg->access->addr) {
+ case A_EFUSE_AES_CRC:
+ case A_EFUSE_AES_USR_KEY0_CRC:
+ case A_EFUSE_AES_USR_KEY1_CRC:
+ *(uint32_t *)reg->data = reg->access->reset;
+ return;
+ }
+
+ register_reset(reg);
+}
+
+static void efuse_ctrl_reset(DeviceState *dev)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(dev);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ efuse_ctrl_register_reset(&s->regs_info[i]);
+ }
+
+ efuse_anchor_bits_check(s);
+ efuse_data_sync(s);
+ efuse_imr_update_irq(s);
+}
+
+static const MemoryRegionOps efuse_ctrl_ops = {
+ .read = register_read_memory,
+ .write = efuse_ctrl_reg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void efuse_ctrl_realize(DeviceState *dev, Error **errp)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(dev);
+ const char *prefix = object_get_canonical_path(OBJECT(dev));
+
+ if (!s->efuse) {
+ error_setg(&error_abort, "%s: XLN-EFUSE not connected", prefix);
+ }
+
+ /* Sort property-defined pgm-locks for bsearch lookup */
+ efuse_lk_spec_sort(s);
+}
+
+static void efuse_ctrl_init(Object *obj)
+{
+ XlnxVersalEFuseCtrl *s = XILINX_EFUSE_CTRL(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_VERSAL_EFUSE_CTRL, R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), efuse_ctrl_regs_info,
+ ARRAY_SIZE(efuse_ctrl_regs_info),
+ s->regs_info, s->regs,
+ &efuse_ctrl_ops,
+ XILINX_EFUSE_CTRL_ERR_DEBUG,
+ R_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ 0x0,
+ ®_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq_efuse_imr);
+}
+
+static const VMStateDescription vmstate_efuse_ctrl = {
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalEFuseCtrl, R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property efuse_ctrl_props[] = {
+ DEFINE_PROP_LINK("efuse",
+ XlnxVersalEFuseCtrl, efuse,
+ TYPE_XLNX_EFUSE, XLNXEFuse *),
+ DEFINE_PROP_ARRAY("pg0-lock",
+ XlnxVersalEFuseCtrl, extra_pg0_lock_n16,
+ extra_pg0_lock.u16, qdev_prop_uint16, uint16_t),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = efuse_ctrl_reset;
+ dc->realize = efuse_ctrl_realize;
+ dc->vmsd = &vmstate_efuse_ctrl;
+ device_class_set_props(dc, efuse_ctrl_props);
+}
+
+static const TypeInfo efuse_ctrl_info = {
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxVersalEFuseCtrl),
+ .class_init = efuse_ctrl_class_init,
+ .instance_init = efuse_ctrl_init,
+};
+
+static void efuse_ctrl_register_types(void)
+{
+ type_register_static(&efuse_ctrl_info);
+}
+
+type_init(efuse_ctrl_register_types)
+
+/*
+ * Retrieve a row, with unreadable bits returned as 0.
+ */
+uint32_t xlnx_versal_efuse_read_row(XLNXEFuse *efuse,
+ uint32_t bit, bool *denied)
+{
+ bool dummy;
+
+ if (!denied) {
+ denied = &dummy;
+ }
+
+ if (bit >= EFUSE_RD_BLOCKED_START && bit <= EFUSE_RD_BLOCKED_END) {
+ *denied = true;
+ return 0;
+ }
+
+ *denied = false;
+ return xlnx_efuse_get_row(efuse, bit);
+}
diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h
new file mode 100644
index 0000000000..c4835cbe67
--- /dev/null
+++ b/include/hw/nvram/xlnx-versal-efuse.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#ifndef XLNX_VERSAL_PMC_EFUSE_H
+#define XLNX_VERSAL_PMC_EFUSE_H
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/nvram/xlnx-efuse.h"
+
+#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse"
+#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache"
+
+#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1)
+
+typedef struct XlnxVersalEFuseCtrl {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ qemu_irq irq_efuse_imr;
+
+ XLNXEFuse *efuse;
+
+ union {
+ uint16_t *u16;
+ XLNXEFuseLkSpec *spec;
+ } extra_pg0_lock;
+ uint32_t extra_pg0_lock_n16;
+
+ uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
+ RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
+} XlnxVersalEFuseCtrl;
+
+typedef struct XlnxVersalEFuseCache {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ XLNXEFuse *efuse;
+} XlnxVersalEFuseCache;
+
+uint32_t xlnx_versal_efuse_read_row(XLNXEFuse *s, uint32_t bit, bool *denied);
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/9] hw/nvram: Introduce Xilinx ZynqMP eFuse device
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
` (2 preceding siblings ...)
2021-08-19 4:03 ` [PATCH 3/9] hw/nvram: Introduce Xilinx Versal eFuse device Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 5/9] hw/nvram: Introduce Xilinx battery-backed ram Tong Ho
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm
Cc: Edgar E . Iglesias, peter.maydell, Sai Pavan Boddu, alistair,
qemu-devel, tong.ho, edgar.iglesias
This implements the Xilinx ZynqMP eFuse, an one-time
field-programmable non-volatile storage device. There is
only one such device in the Xilinx ZynqMP product family.
The command argument:
-drive if=pflash,index=N,...
Can be used to optionally connect the storage array to a
backend storage, such that field-programmed values in one
invocation can be made available to next invocation.
The backend storage must be a seekable binary file, and
its size must be 768 bytes or larger. A file with all
binary 0's is a 'blank'.
The drive 'index' value N has a default value of 3, but
can be changed using command argument:
-global xlnx,efuse.drive-index=N
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/nvram/Kconfig | 5 +
hw/nvram/meson.build | 2 +
hw/nvram/xlnx-zynqmp-efuse.c | 861 +++++++++++++++++++++++++++
include/hw/nvram/xlnx-zynqmp-efuse.h | 45 ++
4 files changed, 913 insertions(+)
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
index e96749ced3..cc3ed789fe 100644
--- a/hw/nvram/Kconfig
+++ b/hw/nvram/Kconfig
@@ -23,3 +23,8 @@ config XLNX_EFUSE_VERSAL
bool
default y if XLNX_VERSAL
select XLNX_EFUSE
+
+config XLNX_EFUSE_ZYNQMP
+ bool
+ default y if XLNX_ZYNQMP
+ select XLNX_EFUSE
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index a432665158..f364520ad5 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -13,6 +13,8 @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
'xlnx-versal-efuse-cache.c',
'xlnx-versal-efuse-ctrl.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
+ 'xlnx-zynqmp-efuse.c'))
if 'CONFIG_XLNX_BBRAM' in config_all or \
'CONFIG_XLNX_EFUSE' in config_all
softmmu_ss.add(files('xlnx-efuse-crc.c'))
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
new file mode 100644
index 0000000000..3591577498
--- /dev/null
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
@@ -0,0 +1,861 @@
+/*
+ * QEMU model of the ZynqMP eFuse
+ *
+ * Copyright (c) 2015 Xilinx Inc.
+ *
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
+ * Partially autogenerated by xregqemu.py 2015-01-02.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
+
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+
+#ifndef ZYNQMP_EFUSE_ERR_DEBUG
+#define ZYNQMP_EFUSE_ERR_DEBUG 0
+#endif
+
+#define ZYNQMP_EFUSE(obj) \
+ OBJECT_CHECK(XlnxZynqMPEFuse, (obj), TYPE_XLNX_ZYNQMP_EFUSE)
+
+REG32(WR_LOCK, 0x0)
+ FIELD(WR_LOCK, LOCK, 0, 16)
+REG32(CFG, 0x4)
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
+ FIELD(CFG, MARGIN_RD, 2, 2)
+ FIELD(CFG, PGM_EN, 1, 1)
+ FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
+REG32(STATUS, 0x8)
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
+ FIELD(STATUS, CACHE_DONE, 5, 1)
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
+ FIELD(STATUS, EFUSE_3_TBIT, 2, 1)
+ FIELD(STATUS, EFUSE_2_TBIT, 1, 1)
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
+REG32(EFUSE_PGM_ADDR, 0xc)
+ FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2)
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 6)
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
+REG32(EFUSE_RD_ADDR, 0x10)
+ FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2)
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 6)
+REG32(EFUSE_RD_DATA, 0x14)
+REG32(TPGM, 0x18)
+ FIELD(TPGM, VALUE, 0, 16)
+REG32(TRD, 0x1c)
+ FIELD(TRD, VALUE, 0, 8)
+REG32(TSU_H_PS, 0x20)
+ FIELD(TSU_H_PS, VALUE, 0, 8)
+REG32(TSU_H_PS_CS, 0x24)
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
+REG32(TSU_H_CS, 0x2c)
+ FIELD(TSU_H_CS, VALUE, 0, 4)
+REG32(EFUSE_ISR, 0x30)
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
+REG32(EFUSE_IMR, 0x34)
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
+REG32(EFUSE_IER, 0x38)
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
+REG32(EFUSE_IDR, 0x3c)
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
+REG32(EFUSE_CACHE_LOAD, 0x40)
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
+REG32(EFUSE_PGM_LOCK, 0x44)
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
+REG32(EFUSE_AES_CRC, 0x48)
+REG32(EFUSE_TBITS_PRGRMG_EN, 0x100)
+ FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1)
+REG32(DNA_0, 0x100c)
+REG32(DNA_1, 0x1010)
+REG32(DNA_2, 0x1014)
+REG32(IPDISABLE, 0x1018)
+ FIELD(IPDISABLE, VCU_DIS, 8, 1)
+ FIELD(IPDISABLE, GPU_DIS, 5, 1)
+ FIELD(IPDISABLE, APU3_DIS, 3, 1)
+ FIELD(IPDISABLE, APU2_DIS, 2, 1)
+ FIELD(IPDISABLE, APU1_DIS, 1, 1)
+ FIELD(IPDISABLE, APU0_DIS, 0, 1)
+REG32(SYSOSC_CTRL, 0x101c)
+ FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1)
+REG32(USER_0, 0x1020)
+REG32(USER_1, 0x1024)
+REG32(USER_2, 0x1028)
+REG32(USER_3, 0x102c)
+REG32(USER_4, 0x1030)
+REG32(USER_5, 0x1034)
+REG32(USER_6, 0x1038)
+REG32(USER_7, 0x103c)
+REG32(MISC_USER_CTRL, 0x1040)
+ FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1)
+ FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1)
+ FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1)
+ FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1)
+REG32(ROM_RSVD, 0x1044)
+ FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3)
+REG32(PUF_CHASH, 0x1050)
+REG32(PUF_MISC, 0x1054)
+ FIELD(PUF_MISC, REGISTER_DIS, 31, 1)
+ FIELD(PUF_MISC, SYN_WRLK, 30, 1)
+ FIELD(PUF_MISC, SYN_INVLD, 29, 1)
+ FIELD(PUF_MISC, TEST2_DIS, 28, 1)
+ FIELD(PUF_MISC, UNUSED27, 27, 1)
+ FIELD(PUF_MISC, UNUSED26, 26, 1)
+ FIELD(PUF_MISC, UNUSED25, 25, 1)
+ FIELD(PUF_MISC, UNUSED24, 24, 1)
+ FIELD(PUF_MISC, AUX, 0, 24)
+REG32(SEC_CTRL, 0x1058)
+ FIELD(SEC_CTRL, PPK1_INVLD, 30, 2)
+ FIELD(SEC_CTRL, PPK1_WRLK, 29, 1)
+ FIELD(SEC_CTRL, PPK0_INVLD, 27, 2)
+ FIELD(SEC_CTRL, PPK0_WRLK, 26, 1)
+ FIELD(SEC_CTRL, RSA_EN, 11, 15)
+ FIELD(SEC_CTRL, SEC_LOCK, 10, 1)
+ FIELD(SEC_CTRL, PROG_GATE_2, 9, 1)
+ FIELD(SEC_CTRL, PROG_GATE_1, 8, 1)
+ FIELD(SEC_CTRL, PROG_GATE_0, 7, 1)
+ FIELD(SEC_CTRL, DFT_DIS, 6, 1)
+ FIELD(SEC_CTRL, JTAG_DIS, 5, 1)
+ FIELD(SEC_CTRL, ERROR_DIS, 4, 1)
+ FIELD(SEC_CTRL, BBRAM_DIS, 3, 1)
+ FIELD(SEC_CTRL, ENC_ONLY, 2, 1)
+ FIELD(SEC_CTRL, AES_WRLK, 1, 1)
+ FIELD(SEC_CTRL, AES_RDLK, 0, 1)
+REG32(SPK_ID, 0x105c)
+REG32(PPK0_0, 0x10a0)
+REG32(PPK0_1, 0x10a4)
+REG32(PPK0_2, 0x10a8)
+REG32(PPK0_3, 0x10ac)
+REG32(PPK0_4, 0x10b0)
+REG32(PPK0_5, 0x10b4)
+REG32(PPK0_6, 0x10b8)
+REG32(PPK0_7, 0x10bc)
+REG32(PPK0_8, 0x10c0)
+REG32(PPK0_9, 0x10c4)
+REG32(PPK0_10, 0x10c8)
+REG32(PPK0_11, 0x10cc)
+REG32(PPK1_0, 0x10d0)
+REG32(PPK1_1, 0x10d4)
+REG32(PPK1_2, 0x10d8)
+REG32(PPK1_3, 0x10dc)
+REG32(PPK1_4, 0x10e0)
+REG32(PPK1_5, 0x10e4)
+REG32(PPK1_6, 0x10e8)
+REG32(PPK1_7, 0x10ec)
+REG32(PPK1_8, 0x10f0)
+REG32(PPK1_9, 0x10f4)
+REG32(PPK1_10, 0x10f8)
+REG32(PPK1_11, 0x10fc)
+
+#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN)
+#define R_MAX (R_PPK1_11 + 1)
+
+/* #define EFUSE_XOSC 26 */
+
+/*
+ * eFUSE layout references:
+ * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
+ */
+#define EFUSE_AES_RDLK BIT_POS(22, 0)
+#define EFUSE_AES_WRLK BIT_POS(22, 1)
+#define EFUSE_ENC_ONLY BIT_POS(22, 2)
+#define EFUSE_BBRAM_DIS BIT_POS(22, 3)
+#define EFUSE_ERROR_DIS BIT_POS(22, 4)
+#define EFUSE_JTAG_DIS BIT_POS(22, 5)
+#define EFUSE_DFT_DIS BIT_POS(22, 6)
+#define EFUSE_PROG_GATE_0 BIT_POS(22, 7)
+#define EFUSE_PROG_GATE_1 BIT_POS(22, 7)
+#define EFUSE_PROG_GATE_2 BIT_POS(22, 9)
+#define EFUSE_SEC_LOCK BIT_POS(22, 10)
+#define EFUSE_RSA_EN BIT_POS(22, 11)
+#define EFUSE_RSA_EN14 BIT_POS(22, 25)
+#define EFUSE_PPK0_WRLK BIT_POS(22, 26)
+#define EFUSE_PPK0_INVLD BIT_POS(22, 27)
+#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28)
+#define EFUSE_PPK1_WRLK BIT_POS(22, 29)
+#define EFUSE_PPK1_INVLD BIT_POS(22, 30)
+#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31)
+
+/* Areas. */
+#define EFUSE_TRIM_START BIT_POS(1, 0)
+#define EFUSE_TRIM_END BIT_POS(1, 30)
+#define EFUSE_DNA_START BIT_POS(3, 0)
+#define EFUSE_DNA_END BIT_POS(5, 31)
+#define EFUSE_AES_START BIT_POS(24, 0)
+#define EFUSE_AES_END BIT_POS(31, 31)
+#define EFUSE_ROM_START BIT_POS(17, 0)
+#define EFUSE_ROM_END BIT_POS(17, 31)
+#define EFUSE_IPDIS_START BIT_POS(6, 0)
+#define EFUSE_IPDIS_END BIT_POS(6, 31)
+#define EFUSE_USER_START BIT_POS(8, 0)
+#define EFUSE_USER_END BIT_POS(15, 31)
+#define EFUSE_BISR_START BIT_POS(32, 0)
+#define EFUSE_BISR_END BIT_POS(39, 31)
+
+#define EFUSE_USER_CTRL_START BIT_POS(16, 0)
+#define EFUSE_USER_CTRL_END BIT_POS(16, 16)
+#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17))
+
+#define EFUSE_PUF_CHASH_START BIT_POS(20, 0)
+#define EFUSE_PUF_CHASH_END BIT_POS(20, 31)
+#define EFUSE_PUF_MISC_START BIT_POS(21, 0)
+#define EFUSE_PUF_MISC_END BIT_POS(21, 31)
+#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30)
+
+#define EFUSE_SPK_START BIT_POS(23, 0)
+#define EFUSE_SPK_END BIT_POS(23, 31)
+
+#define EFUSE_PPK0_START BIT_POS(40, 0)
+#define EFUSE_PPK0_END BIT_POS(51, 31)
+#define EFUSE_PPK1_START BIT_POS(52, 0)
+#define EFUSE_PPK1_END BIT_POS(63, 31)
+
+#define EFUSE_CACHE_FLD(s, reg, field) \
+ ARRAY_FIELD_DP32((s)->regs, reg, field, \
+ (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
+ >> (EFUSE_ ## field % 32)))
+
+#define EFUSE_CACHE_BIT(s, reg, field) \
+ ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
+ EFUSE_ ## field))
+
+#define FBIT_UNKNOWN (~0)
+
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));
+
+static void update_tbit_status(XlnxZynqMPEFuse *s)
+{
+ unsigned int check = xlnx_efuse_tbits_check(s->efuse);
+ uint32_t val = s->regs[R_STATUS];
+
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1)));
+ val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2)));
+
+ s->regs[R_STATUS] = val;
+}
+
+/* Update the u32 array from efuse bits. Slow but simple approach. */
+static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start,
+ unsigned int f_start, unsigned int f_end,
+ unsigned int f_written)
+{
+ uint32_t *u32 = &s->regs[r_start];
+ unsigned int fbit, wbits = 0, u32_off = 0;
+
+ /* Avoid working on bits that are not relevant. */
+ if (f_written != FBIT_UNKNOWN
+ && (f_written < f_start || f_written > f_end)) {
+ return;
+ }
+
+ for (fbit = f_start; fbit <= f_end; fbit++, wbits++) {
+ if (wbits == 32) {
+ /* Update the key offset. */
+ u32_off += 1;
+ wbits = 0;
+ }
+ u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits;
+ }
+}
+
+/*
+ * Keep the syncs in bit order so we can bail out for the
+ * slower ones.
+ */
+static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit)
+{
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK);
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK);
+
+ EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN);
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD);
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD);
+
+ /* Update the tbits. */
+ update_tbit_status(s);
+
+ /* Sync the various areas. */
+ s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse,
+ EFUSE_USER_CTRL_START)
+ & EFUSE_USER_CTRL_MASK;
+ s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START);
+ s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START);
+
+ cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit);
+
+ if (bit < EFUSE_AES_START) {
+ return;
+ }
+
+ cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit);
+ cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit);
+ cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit);
+ cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit);
+ cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit);
+ cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit);
+}
+
+static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s)
+{
+ bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR];
+ qemu_set_irq(s->irq, pending);
+}
+
+static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(reg->opaque);
+ zynqmp_efuse_update_irq(s);
+}
+
+static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_EFUSE_IMR] |= val;
+ zynqmp_efuse_update_irq(s);
+ return 0;
+}
+
+static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_EFUSE_IMR] &= ~val;
+ zynqmp_efuse_update_irq(s);
+ return 0;
+}
+
+static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(reg->opaque);
+ unsigned bit = val64;
+ unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE);
+ bool puf_prot = false;
+ const char *errmsg = NULL;
+
+ /* Allow only valid array, and adjust for skipped array 1 */
+ switch (page) {
+ case 0:
+ break;
+ case 2 ... 3:
+ bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1);
+ puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK);
+ break;
+ default:
+ errmsg = "Invalid address";
+ goto pgm_done;
+ }
+
+ if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) {
+ errmsg = "Array write-locked";
+ goto pgm_done;
+ }
+
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
+ errmsg = "Array pgm-disabled";
+ goto pgm_done;
+ }
+
+ if (puf_prot) {
+ errmsg = "PUF_HD-store write-locked";
+ goto pgm_done;
+ }
+
+ if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK)
+ && bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) {
+ errmsg = "AES key-store Write-locked";
+ goto pgm_done;
+ }
+
+ if (!xlnx_efuse_set_bit(s->efuse, bit)) {
+ errmsg = "Write failed";
+ }
+
+ pgm_done:
+ if (!errmsg) {
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0);
+ } else {
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s - eFuse write error: %s; addr=0x%x\n",
+ object_get_canonical_path(OBJECT(s)),
+ errmsg, (unsigned)val64);
+ }
+
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
+ zynqmp_efuse_update_irq(s);
+}
+
+static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(reg->opaque);
+
+ /*
+ * Grant reads only to allowed bits; reference sources:
+ * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow()
+ * 2/ UG1085, v2.0, table 12-13
+ * (note: enumerates the masks as <first, last> per described in
+ * references to avoid mental translation).
+ */
+#define COL_MASK(L_, H_) \
+ ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_))))
+
+ static const uint32_t ary0_col_mask[] = {
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */
+ [0] = COL_MASK(28, 31),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */
+ [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31),
+ [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31),
+ [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31),
+ [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */
+ [16] = COL_MASK(0, 7) | COL_MASK(10, 16),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */
+ [17] = COL_MASK(0, 2),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */
+ [20] = COL_MASK(0, 31),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */
+ [21] = COL_MASK(0, 23) | COL_MASK(29, 31),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */
+ [22] = COL_MASK(0, 31),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */
+ [23] = COL_MASK(0, 31),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */
+ [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31),
+ [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31),
+ [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31),
+ [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31),
+ [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31),
+ [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31),
+
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */
+ [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31),
+ [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31),
+ [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31),
+ [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31),
+ [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31),
+ [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31),
+ };
+
+ uint32_t col_mask = COL_MASK(0, 31);
+#undef COL_MASK
+
+ uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR];
+ uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE);
+ uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW);
+
+ switch (efuse_ary) {
+ case 0: /* Various */
+ if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) {
+ goto denied;
+ }
+
+ col_mask = ary0_col_mask[efuse_row];
+ if (!col_mask) {
+ goto denied;
+ }
+ break;
+ case 2: /* PUF helper data, adjust for skipped array 1 */
+ case 3:
+ val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1);
+ break;
+ default:
+ goto denied;
+ }
+
+ s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask;
+
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0);
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
+ zynqmp_efuse_update_irq(s);
+ return;
+
+ denied:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Denied efuse read from array %u, row %u\n",
+ object_get_canonical_path(OBJECT(s)),
+ efuse_ary, efuse_row);
+
+ s->regs[R_EFUSE_RD_DATA] = 0;
+
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0);
+ zynqmp_efuse_update_irq(s);
+}
+
+static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(reg->opaque);
+ bool ok;
+
+ ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START);
+
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0));
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1);
+
+ s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */
+}
+
+static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg,
+ uint64_t valu64)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(reg->opaque);
+
+ if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
+ zynqmp_efuse_update_irq(s);
+ }
+
+ return 0;
+}
+
+static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
+{
+ return val == 0xDF0D ? 0 : 1;
+}
+
+static RegisterAccessInfo zynqmp_efuse_regs_info[] = {
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
+ .reset = 0x1,
+ .pre_write = zynqmp_efuse_wr_lock_prew,
+ },{ .name = "CFG", .addr = A_CFG,
+ },{ .name = "STATUS", .addr = A_STATUS,
+ .rsvd = 0x8,
+ .ro = 0xff,
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
+ .post_write = zynqmp_efuse_pgm_addr_postw
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
+ .rsvd = 0x1f,
+ .post_write = zynqmp_efuse_rd_addr_postw,
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
+ .ro = 0xffffffff,
+ },{ .name = "TPGM", .addr = A_TPGM,
+ },{ .name = "TRD", .addr = A_TRD,
+ .reset = 0x1b,
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
+ .reset = 0xff,
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
+ .reset = 0xb,
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
+ .reset = 0x7,
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
+ .rsvd = 0x7fffffe0,
+ .w1c = 0x8000001f,
+ .post_write = zynqmp_efuse_isr_postw,
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
+ .reset = 0x8000001f,
+ .rsvd = 0x7fffffe0,
+ .ro = 0xffffffff,
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
+ .rsvd = 0x7fffffe0,
+ .pre_write = zynqmp_efuse_ier_prew,
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
+ .rsvd = 0x7fffffe0,
+ .pre_write = zynqmp_efuse_idr_prew,
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
+ .pre_write = zynqmp_efuse_cache_load_prew,
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
+ .post_write = zynqmp_efuse_aes_crc_postw,
+ },{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN,
+ .reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK,
+ },{ .name = "DNA_0", .addr = A_DNA_0,
+ .ro = 0xffffffff,
+ },{ .name = "DNA_1", .addr = A_DNA_1,
+ .ro = 0xffffffff,
+ },{ .name = "DNA_2", .addr = A_DNA_2,
+ .ro = 0xffffffff,
+ },{ .name = "IPDISABLE", .addr = A_IPDISABLE,
+ .ro = 0xffffffff,
+ },{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL,
+ .ro = 0xffffffff,
+ },{ .name = "USER_0", .addr = A_USER_0,
+ .ro = 0xffffffff,
+ },{ .name = "USER_1", .addr = A_USER_1,
+ .ro = 0xffffffff,
+ },{ .name = "USER_2", .addr = A_USER_2,
+ .ro = 0xffffffff,
+ },{ .name = "USER_3", .addr = A_USER_3,
+ .ro = 0xffffffff,
+ },{ .name = "USER_4", .addr = A_USER_4,
+ .ro = 0xffffffff,
+ },{ .name = "USER_5", .addr = A_USER_5,
+ .ro = 0xffffffff,
+ },{ .name = "USER_6", .addr = A_USER_6,
+ .ro = 0xffffffff,
+ },{ .name = "USER_7", .addr = A_USER_7,
+ .ro = 0xffffffff,
+ },{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL,
+ .ro = 0xffffffff,
+ },{ .name = "ROM_RSVD", .addr = A_ROM_RSVD,
+ .ro = 0xffffffff,
+ },{ .name = "PUF_CHASH", .addr = A_PUF_CHASH,
+ .ro = 0xffffffff,
+ },{ .name = "PUF_MISC", .addr = A_PUF_MISC,
+ .ro = 0xffffffff,
+ },{ .name = "SEC_CTRL", .addr = A_SEC_CTRL,
+ .ro = 0xffffffff,
+ },{ .name = "SPK_ID", .addr = A_SPK_ID,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_0", .addr = A_PPK0_0,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_1", .addr = A_PPK0_1,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_2", .addr = A_PPK0_2,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_3", .addr = A_PPK0_3,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_4", .addr = A_PPK0_4,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_5", .addr = A_PPK0_5,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_6", .addr = A_PPK0_6,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_7", .addr = A_PPK0_7,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_8", .addr = A_PPK0_8,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_9", .addr = A_PPK0_9,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_10", .addr = A_PPK0_10,
+ .ro = 0xffffffff,
+ },{ .name = "PPK0_11", .addr = A_PPK0_11,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_0", .addr = A_PPK1_0,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_1", .addr = A_PPK1_1,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_2", .addr = A_PPK1_2,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_3", .addr = A_PPK1_3,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_4", .addr = A_PPK1_4,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_5", .addr = A_PPK1_5,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_6", .addr = A_PPK1_6,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_7", .addr = A_PPK1_7,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_8", .addr = A_PPK1_8,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_9", .addr = A_PPK1_9,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_10", .addr = A_PPK1_10,
+ .ro = 0xffffffff,
+ },{ .name = "PPK1_11", .addr = A_PPK1_11,
+ .ro = 0xffffffff,
+ }
+};
+
+static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ RegisterInfoArray *reg_array = opaque;
+ XlnxZynqMPEFuse *s;
+ Object *dev;
+
+ assert(reg_array != NULL);
+
+ dev = reg_array->mem.owner;
+ assert(dev);
+
+ s = ZYNQMP_EFUSE(dev);
+
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
+ object_get_canonical_path(OBJECT(s)), (long)addr);
+ } else {
+ register_write_memory(opaque, addr, data, size);
+ }
+}
+
+static const MemoryRegionOps zynqmp_efuse_ops = {
+ .read = register_read_memory,
+ .write = zynqmp_efuse_reg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void zynqmp_efuse_register_reset(RegisterInfo *reg)
+{
+ if (!reg->data || !reg->access) {
+ return;
+ }
+
+ /* Reset must not trigger some registers' writers */
+ switch (reg->access->addr) {
+ case A_EFUSE_AES_CRC:
+ *(uint32_t *)reg->data = reg->access->reset;
+ return;
+ }
+
+ register_reset(reg);
+}
+
+static void zynqmp_efuse_reset(DeviceState *dev)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(dev);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ zynqmp_efuse_register_reset(&s->regs_info[i]);
+ }
+
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
+ zynqmp_efuse_update_irq(s);
+}
+
+static void zynqmp_efuse_realize(DeviceState *dev, Error **errp)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(dev);
+ const char *prefix = object_get_canonical_path(OBJECT(dev));
+
+ if (!s->efuse) {
+ error_setg(&error_abort, "%s: XLN-EFUSE not connected", prefix);
+ }
+
+ s->efuse->dev = dev;
+}
+
+static void zynqmp_efuse_init(Object *obj)
+{
+ XlnxZynqMPEFuse *s = ZYNQMP_EFUSE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_EFUSE, R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info,
+ ARRAY_SIZE(zynqmp_efuse_regs_info),
+ s->regs_info, s->regs,
+ &zynqmp_efuse_ops,
+ ZYNQMP_EFUSE_ERR_DEBUG,
+ R_MAX * 4);
+ memory_region_add_subregion(&s->iomem, 0, ®_array->mem);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static const VMStateDescription vmstate_efuse = {
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property zynqmp_efuse_props[] = {
+ DEFINE_PROP_LINK("efuse",
+ XlnxZynqMPEFuse, efuse,
+ TYPE_XLNX_EFUSE, XLNXEFuse *),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = zynqmp_efuse_reset;
+ dc->realize = zynqmp_efuse_realize;
+ dc->vmsd = &vmstate_efuse;
+ device_class_set_props(dc, zynqmp_efuse_props);
+}
+
+
+static const TypeInfo efuse_info = {
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqMPEFuse),
+ .class_init = zynqmp_efuse_class_init,
+ .instance_init = zynqmp_efuse_init,
+};
+
+static void efuse_register_types(void)
+{
+ type_register_static(&efuse_info);
+}
+
+type_init(efuse_register_types)
diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h
new file mode 100644
index 0000000000..97ac521ae4
--- /dev/null
+++ b/include/hw/nvram/xlnx-zynqmp-efuse.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021 Xilinx Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#ifndef XLNX_ZYNQMP_EFUSE_H
+#define XLNX_ZYNQMP_EFUSE_H
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/nvram/xlnx-efuse.h"
+
+#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse"
+
+#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1)
+
+typedef struct XlnxZynqMPEFuse {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ XLNXEFuse *efuse;
+ uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX];
+ RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX];
+} XlnxZynqMPEFuse;
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 5/9] hw/nvram: Introduce Xilinx battery-backed ram
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
` (3 preceding siblings ...)
2021-08-19 4:03 ` [PATCH 4/9] hw/nvram: Introduce Xilinx ZynqMP " Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 6/9] hw/arm: xlnx-versal: Add Xilinx BBRAM device Tong Ho
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm
Cc: Edgar E . Iglesias, peter.maydell, Sai Pavan Boddu, alistair,
qemu-devel, tong.ho, edgar.iglesias
This device is present in Versal and ZynqMP product
families to store a 256-bit encryption key.
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/nvram/Kconfig | 4 +
hw/nvram/meson.build | 1 +
hw/nvram/xlnx-bbram.c | 536 ++++++++++++++++++++++++++++++++++
include/hw/nvram/xlnx-bbram.h | 55 ++++
4 files changed, 596 insertions(+)
create mode 100644 hw/nvram/xlnx-bbram.c
create mode 100644 include/hw/nvram/xlnx-bbram.h
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
index cc3ed789fe..a8c5e9227e 100644
--- a/hw/nvram/Kconfig
+++ b/hw/nvram/Kconfig
@@ -28,3 +28,7 @@ config XLNX_EFUSE_ZYNQMP
bool
default y if XLNX_ZYNQMP
select XLNX_EFUSE
+
+config XLNX_BBRAM
+ bool
+ default y if (XLNX_VERSAL || XLNX_ZYNQMP)
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index f364520ad5..0a1676d37a 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -9,6 +9,7 @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c', 'xlnx-efuse-crc.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
'xlnx-versal-efuse-cache.c',
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
new file mode 100644
index 0000000000..d560dcdfa8
--- /dev/null
+++ b/hw/nvram/xlnx-bbram.c
@@ -0,0 +1,536 @@
+/*
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
+ *
+ * Copyright (c) 2014-2021 Xilinx Inc.
+ *
+ * Autogenerated by xregqemu.py 2020-02-06.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nvram/xlnx-bbram.h"
+
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "sysemu/blockdev.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/nvram/xlnx-efuse.h"
+
+#ifndef XLNX_BBRAM_ERR_DEBUG
+#define XLNX_BBRAM_ERR_DEBUG 0
+#endif
+
+#define XLNX_BBRAM(obj) \
+ OBJECT_CHECK(XlnxBBRam, (obj), TYPE_XLNX_BBRAM)
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (XLNX_BBRAM_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0)
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+REG32(BBRAM_STATUS, 0x0)
+ FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1)
+ FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1)
+ FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1)
+ FIELD(BBRAM_STATUS, PGM_MODE, 0, 1)
+REG32(BBRAM_CTRL, 0x4)
+ FIELD(BBRAM_CTRL, ZEROIZE, 0, 1)
+REG32(PGM_MODE, 0x8)
+REG32(BBRAM_AES_CRC, 0xc)
+REG32(BBRAM_0, 0x10)
+REG32(BBRAM_1, 0x14)
+REG32(BBRAM_2, 0x18)
+REG32(BBRAM_3, 0x1c)
+REG32(BBRAM_4, 0x20)
+REG32(BBRAM_5, 0x24)
+REG32(BBRAM_6, 0x28)
+REG32(BBRAM_7, 0x2c)
+REG32(BBRAM_8, 0x30)
+REG32(BBRAM_SLVERR, 0x34)
+ FIELD(BBRAM_SLVERR, ENABLE, 0, 1)
+REG32(BBRAM_ISR, 0x38)
+ FIELD(BBRAM_ISR, APB_SLVERR, 0, 1)
+REG32(BBRAM_IMR, 0x3c)
+ FIELD(BBRAM_IMR, APB_SLVERR, 0, 1)
+REG32(BBRAM_IER, 0x40)
+ FIELD(BBRAM_IER, APB_SLVERR, 0, 1)
+REG32(BBRAM_IDR, 0x44)
+ FIELD(BBRAM_IDR, APB_SLVERR, 0, 1)
+REG32(BBRAM_MSW_LOCK, 0x4c)
+ FIELD(BBRAM_MSW_LOCK, VAL, 0, 1)
+
+#define R_MAX (R_BBRAM_MSW_LOCK + 1)
+
+#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
+
+#define BBRAM_PGM_MAGIC 0x757bdf0d
+
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
+
+static bool bbram_msw_locked(XlnxBBRam *s)
+{
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0;
+}
+
+static bool bbram_pgm_enabled(XlnxBBRam *s)
+{
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0;
+}
+
+static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
+{
+ Error *errp;
+
+ error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
+ blk_name(s->blk), detail);
+ error_report("%s", error_get_pretty(errp));
+ error_free(errp);
+
+ g_free(detail);
+}
+
+static void bbram_bdrv_read(XlnxBBRam *s)
+{
+ const char *prefix = object_get_canonical_path(OBJECT(s));
+ uint32_t *ram = &s->regs[R_BBRAM_0];
+ int nr = RAM_MAX;
+ int rc;
+
+ assert(s->blk);
+
+ s->blk_ro = !blk_supports_write_perm(s->blk);
+ if (s->blk_ro) {
+ warn_report("%s: update not saved: backstore is read-only", prefix);
+ }
+ blk_set_perm(s->blk,
+ (BLK_PERM_CONSISTENT_READ | (s->blk_ro ? 0 : BLK_PERM_WRITE)),
+ BLK_PERM_ALL, &error_abort);
+
+ rc = blk_pread(s->blk, 0, ram, nr);
+ if (rc < 0) {
+ bbram_bdrv_error(s, rc, g_strdup_printf("read %u bytes", nr));
+ error_setg(&error_abort, "%s: Unable to read-out contents."
+ "backing file too small? Expecting %u bytes", prefix, nr);
+ }
+
+ if (const_le32(0x1234) != 0x1234) {
+ /* Convert from little-endian backstore for each 32-bit row */
+ nr /= 4;
+ while (nr--) {
+ ram[nr] = le32_to_cpu(ram[nr]);
+ }
+ }
+}
+
+static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr)
+{
+ uint32_t le32;
+ unsigned offset;
+ int rc;
+
+ assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8);
+
+ /* Backstore is always in little-endian */
+ le32 = cpu_to_le32(s->regs[hwaddr / 4]);
+
+ /* Update zeroized flag */
+ if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) {
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0);
+ }
+
+ if (!s->blk || s->blk_ro) {
+ return;
+ }
+
+ offset = hwaddr - A_BBRAM_0;
+ rc = blk_pwrite(s->blk, offset, &le32, 4, 0);
+ if (rc < 0) {
+ bbram_bdrv_error(s, rc, g_strdup_printf("write to %u", offset));
+ }
+}
+
+static void bbram_bdrv_zero(XlnxBBRam *s)
+{
+ int rc;
+
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1);
+
+ if (!s->blk || s->blk_ro) {
+ return;
+ }
+
+ rc = blk_make_zero(s->blk, 0);
+ if (rc < 0) {
+ bbram_bdrv_error(s, rc, g_strdup("zeroizing"));
+ }
+
+ /* Restore bbram8 if it is non-zero */
+ if (s->regs[R_BBRAM_8]) {
+ bbram_bdrv_sync(s, A_BBRAM_8);
+ }
+}
+
+static void bbram_zeroize(XlnxBBRam *s)
+{
+ int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */
+
+ DB_PRINT("Zeroing out the key\n");
+ memset(&s->regs[R_BBRAM_0], 0, nr);
+ bbram_bdrv_zero(s);
+}
+
+static void bbram_update_irq(XlnxBBRam *s)
+{
+ bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR];
+
+ DB_PRINT("Setting the interrupt: %d\n", pending);
+ qemu_set_irq(s->irq_bbram, pending);
+}
+
+static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+ uint32_t val = val64;
+
+ if (val & R_BBRAM_CTRL_ZEROIZE_MASK) {
+ bbram_zeroize(s);
+ /* The bit is self clearing */
+ s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK;
+ }
+}
+
+static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+ uint32_t val = val64;
+
+ if (val == BBRAM_PGM_MAGIC) {
+ bbram_zeroize(s);
+
+ /* The status bit is cleared only by POR */
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1);
+ }
+}
+
+static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+ uint32_t calc_crc;
+
+ if (!bbram_pgm_enabled(s)) {
+ /* We are not in programming mode, don't do anything */
+ return;
+ }
+
+ /* Perform the AES integrity check */
+ s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK;
+
+ /*
+ * Set check status.
+ *
+ * ZynqMP BBRAM check has a zero-u32 prepended; see:
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311
+ */
+ calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0],
+ (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads);
+
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS,
+ (s->regs[R_BBRAM_AES_CRC] == calc_crc));
+}
+
+static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+ uint32_t original_data = *(uint32_t *) reg->data;
+
+ if (bbram_pgm_enabled(s)) {
+ DB_PRINT("Writing value: 0x%"HWADDR_PRIx"\n", val64);
+ return val64;
+ } else {
+ /* We are not in programming mode, don't do anything */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Not in programming mode, dropping the write\n");
+ return original_data;
+ }
+}
+
+static void bbram_key_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+
+ bbram_bdrv_sync(s, reg->access->addr);
+}
+
+static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val)
+{
+ return 0;
+}
+
+static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+
+ return s->bbram8_wo ? bbram_wo_postr(reg, val) : val;
+}
+
+static bool bbram_r8_readonly(XlnxBBRam *s)
+{
+ return !bbram_pgm_enabled(s) || bbram_msw_locked(s);
+}
+
+static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+
+ if (bbram_r8_readonly(s)) {
+ val64 = *(uint32_t *)reg->data;
+ }
+
+ return val64;
+}
+
+static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+
+ if (!bbram_r8_readonly(s)) {
+ bbram_bdrv_sync(s, A_BBRAM_8);
+ }
+}
+
+static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+
+ /* Never lock if bbram8 is wo; and, only POR can clear the lock */
+ if (s->bbram8_wo) {
+ val64 = 0;
+ } else {
+ val64 |= s->regs[R_BBRAM_MSW_LOCK];
+ }
+
+ return val64;
+}
+
+static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+
+ bbram_update_irq(s);
+}
+
+static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_BBRAM_IMR] &= ~val;
+ bbram_update_irq(s);
+ return 0;
+}
+
+static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_BBRAM_IMR] |= val;
+ bbram_update_irq(s);
+ return 0;
+}
+
+static RegisterAccessInfo bbram_ctrl_regs_info[] = {
+ { .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS,
+ .rsvd = 0xee,
+ .ro = 0x3ff,
+ },{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL,
+ .post_write = bbram_ctrl_postw,
+ },{ .name = "PGM_MODE", .addr = A_PGM_MODE,
+ .post_write = bbram_pgm_mode_postw,
+ },{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC,
+ .post_write = bbram_aes_crc_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_0", .addr = A_BBRAM_0,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_1", .addr = A_BBRAM_1,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_2", .addr = A_BBRAM_2,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_3", .addr = A_BBRAM_3,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_4", .addr = A_BBRAM_4,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_5", .addr = A_BBRAM_5,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_6", .addr = A_BBRAM_6,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_7", .addr = A_BBRAM_7,
+ .pre_write = bbram_key_prew,
+ .post_write = bbram_key_postw,
+ .post_read = bbram_wo_postr,
+ },{ .name = "BBRAM_8", .addr = A_BBRAM_8,
+ .pre_write = bbram_r8_prew,
+ .post_write = bbram_r8_postw,
+ .post_read = bbram_r8_postr,
+ },{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR,
+ .rsvd = ~1,
+ },{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR,
+ .w1c = 0x1,
+ .post_write = bbram_isr_postw,
+ },{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR,
+ .ro = 0x1,
+ },{ .name = "BBRAM_IER", .addr = A_BBRAM_IER,
+ .pre_write = bbram_ier_prew,
+ },{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR,
+ .pre_write = bbram_idr_prew,
+ },{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK,
+ .pre_write = bbram_msw_lock_prew,
+ .ro = ~R_BBRAM_MSW_LOCK_VAL_MASK,
+ }
+};
+
+static void bbram_ctrl_reset(DeviceState *dev)
+{
+ XlnxBBRam *s = XLNX_BBRAM(dev);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ if (i < R_BBRAM_0 || i > R_BBRAM_8) {
+ register_reset(&s->regs_info[i]);
+ }
+ }
+
+ bbram_update_irq(s);
+}
+
+static const MemoryRegionOps bbram_ctrl_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void bbram_ctrl_realize(DeviceState *dev, Error **errp)
+{
+ XlnxBBRam *s = XLNX_BBRAM(dev);
+ DriveInfo *dinfo;
+ BlockBackend *blk;
+
+ if (s->crc_zpads) {
+ s->bbram8_wo = true;
+ }
+
+ if (s->drv_index < 0) {
+ /* Set legacy compatibility */
+ s->drv_index = s->crc_zpads ? 2 : 0;
+ }
+
+ dinfo = drive_get_by_index(IF_PFLASH, s->drv_index);
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
+ if (blk) {
+ qdev_prop_set_drive(dev, "drive", blk);
+ bbram_bdrv_read(s);
+ }
+}
+
+static void bbram_ctrl_init(Object *obj)
+{
+ XlnxBBRam *s = XLNX_BBRAM(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_BBRAM, R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), bbram_ctrl_regs_info,
+ ARRAY_SIZE(bbram_ctrl_regs_info),
+ s->regs_info, s->regs,
+ &bbram_ctrl_ops,
+ XLNX_BBRAM_ERR_DEBUG,
+ R_MAX * 4);
+ memory_region_add_subregion(&s->iomem, 0x0, ®_array->mem);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq_bbram);
+}
+
+static const VMStateDescription vmstate_bbram_ctrl = {
+ .name = TYPE_XLNX_BBRAM,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property bbram_ctrl_props[] = {
+ DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1),
+ DEFINE_PROP_INT32("drive-index", XlnxBBRam, drv_index, -1),
+ DEFINE_PROP_DRIVE("drive", XlnxBBRam, blk),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = bbram_ctrl_reset;
+ dc->realize = bbram_ctrl_realize;
+ dc->vmsd = &vmstate_bbram_ctrl;
+ device_class_set_props(dc, bbram_ctrl_props);
+}
+
+static const TypeInfo bbram_ctrl_info = {
+ .name = TYPE_XLNX_BBRAM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxBBRam),
+ .class_init = bbram_ctrl_class_init,
+ .instance_init = bbram_ctrl_init,
+};
+
+static void bbram_ctrl_register_types(void)
+{
+ type_register_static(&bbram_ctrl_info);
+}
+
+type_init(bbram_ctrl_register_types)
diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
new file mode 100644
index 0000000000..ad6bed18ce
--- /dev/null
+++ b/include/hw/nvram/xlnx-bbram.h
@@ -0,0 +1,55 @@
+/*
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
+ *
+ * Copyright (c) 2015-2021 Xilinx Inc.
+ *
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#ifndef XLNX_BBRAM_H
+#define XLNX_BBRAM_H
+
+#include "qemu/osdep.h"
+#include "sysemu/block-backend.h"
+#include "hw/qdev-core.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+
+#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
+#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
+
+typedef struct XlnxBBram {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ qemu_irq irq_bbram;
+
+ BlockBackend *blk;
+
+ uint32_t crc_zpads;
+ int32_t drv_index;
+ bool bbram8_wo;
+ bool blk_ro;
+
+ uint32_t regs[RMAX_XLNX_BBRAM];
+ RegisterInfo regs_info[RMAX_XLNX_BBRAM];
+} XlnxBBRam;
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6/9] hw/arm: xlnx-versal: Add Xilinx BBRAM device
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
` (4 preceding siblings ...)
2021-08-19 4:03 ` [PATCH 5/9] hw/nvram: Introduce Xilinx battery-backed ram Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 7/9] hw/arm: xlnx-versal: Add Xilinx eFUSE device Tong Ho
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm; +Cc: edgar.iglesias, alistair, tong.ho, qemu-devel, peter.maydell
Connect the support for Versal Battery-Backed RAM (BBRAM)
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/arm/xlnx-versal-virt.c | 21 +++++++++++++++++++++
hw/arm/xlnx-versal.c | 18 ++++++++++++++++++
include/hw/arm/xlnx-versal.h | 5 +++++
3 files changed, 44 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 5bca360dce..d9e2a6a853 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -356,6 +356,26 @@ static void fdt_add_rtc_node(VersalVirt *s)
g_free(name);
}
+static void fdt_add_bbram_node(VersalVirt *s)
+{
+ const char compat[] = TYPE_XLNX_BBRAM;
+ const char interrupt_names[] = "bbram-error";
+ char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL);
+
+ qemu_fdt_add_subnode(s->fdt, name);
+
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+ interrupt_names, sizeof(interrupt_names));
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+ 2, MM_PMC_BBRAM_CTRL,
+ 2, MM_PMC_BBRAM_CTRL_SIZE);
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+ g_free(name);
+}
+
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
{
Error *err = NULL;
@@ -570,6 +590,7 @@ static void versal_virt_init(MachineState *machine)
fdt_add_usb_xhci_nodes(s);
fdt_add_sd_nodes(s);
fdt_add_rtc_node(s);
+ fdt_add_bbram_node(s);
fdt_add_cpu_nodes(s, psci_conduit);
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index fb776834f7..46d7f42a6b 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -312,6 +312,23 @@ static void versal_create_xrams(Versal *s, qemu_irq *pic)
}
}
+static void versal_create_bbram(Versal *s, qemu_irq *pic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
+ sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
+ &error_fatal,
+ "crc-zpads", "0",
+ NULL);
+ sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
+
+ sysbus_realize(sbd, &error_fatal);
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
+ sysbus_mmio_get_region(sbd, 0));
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
@@ -398,6 +415,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_sds(s, pic);
versal_create_rtc(s, pic);
versal_create_xrams(s, pic);
+ versal_create_bbram(s, pic);
versal_map_ddr(s);
versal_unimp(s);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 22a8fa5d11..7719e8c4d2 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -24,6 +24,7 @@
#include "qom/object.h"
#include "hw/usb/xlnx-usb-subsystem.h"
#include "hw/misc/xlnx-versal-xramc.h"
+#include "hw/nvram/xlnx-bbram.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -79,6 +80,7 @@ struct Versal {
} iou;
XlnxZynqMPRTC rtc;
+ XlnxBBRam bbram;
} pmc;
struct {
@@ -105,6 +107,7 @@ struct Versal {
#define VERSAL_GEM1_WAKE_IRQ_0 59
#define VERSAL_ADMA_IRQ_0 60
#define VERSAL_XRAM_IRQ_0 79
+#define VERSAL_BBRAM_APB_IRQ_0 121
#define VERSAL_RTC_APB_ERR_IRQ 121
#define VERSAL_SD0_IRQ_0 126
#define VERSAL_RTC_ALARM_IRQ 142
@@ -170,6 +173,8 @@ struct Versal {
#define MM_PMC_SD0 0xf1040000U
#define MM_PMC_SD0_SIZE 0x10000
+#define MM_PMC_BBRAM_CTRL 0xf11f0000
+#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
#define MM_PMC_CRP 0xf1260000U
#define MM_PMC_CRP_SIZE 0x10000
#define MM_PMC_RTC 0xf12a0000
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 7/9] hw/arm: xlnx-versal: Add Xilinx eFUSE device
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
` (5 preceding siblings ...)
2021-08-19 4:03 ` [PATCH 6/9] hw/arm: xlnx-versal: Add Xilinx BBRAM device Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 8/9] hw/arm: xlnx-zynqmp: Add Xilinx BBRAM device Tong Ho
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm; +Cc: edgar.iglesias, alistair, tong.ho, qemu-devel, peter.maydell
Connect the support for Versal eFUSE one-time field-programmable
bit array.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/arm/xlnx-versal-virt.c | 36 +++++++++++++++++++++++++++++++++
hw/arm/xlnx-versal.c | 39 ++++++++++++++++++++++++++++++++++++
include/hw/arm/xlnx-versal.h | 12 +++++++++++
3 files changed, 87 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index d9e2a6a853..04da6c4517 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -376,6 +376,40 @@ static void fdt_add_bbram_node(VersalVirt *s)
g_free(name);
}
+static void fdt_add_efuse_ctrl_node(VersalVirt *s)
+{
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL;
+ const char interrupt_names[] = "pmc_efuse";
+ char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL);
+
+ qemu_fdt_add_subnode(s->fdt, name);
+
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ,
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+ interrupt_names, sizeof(interrupt_names));
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+ 2, MM_PMC_EFUSE_CTRL,
+ 2, MM_PMC_EFUSE_CTRL_SIZE);
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+ g_free(name);
+}
+
+static void fdt_add_efuse_cache_node(VersalVirt *s)
+{
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE;
+ char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x", MM_PMC_EFUSE_CACHE);
+
+ qemu_fdt_add_subnode(s->fdt, name);
+
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+ 2, MM_PMC_EFUSE_CACHE,
+ 2, MM_PMC_EFUSE_CACHE_SIZE);
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+ g_free(name);
+}
+
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
{
Error *err = NULL;
@@ -591,6 +625,8 @@ static void versal_virt_init(MachineState *machine)
fdt_add_sd_nodes(s);
fdt_add_rtc_node(s);
fdt_add_bbram_node(s);
+ fdt_add_efuse_ctrl_node(s);
+ fdt_add_efuse_cache_node(s);
fdt_add_cpu_nodes(s, psci_conduit);
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 46d7f42a6b..d278d6e0f4 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -329,6 +329,44 @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
}
+static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
+{
+ SysBusDevice *part = SYS_BUS_DEVICE(dev);
+
+ object_property_set_link(OBJECT(part), "efuse",
+ OBJECT(&s->pmc.efuse.bits), &error_abort);
+
+ sysbus_realize(part, &error_abort);
+ memory_region_add_subregion(&s->mr_ps, base,
+ sysbus_mmio_get_region(part, 0));
+}
+
+static void versal_create_efuse(Versal *s, qemu_irq *pic)
+{
+ Object *bits = OBJECT(&s->pmc.efuse.bits);
+ Object *ctrl = OBJECT(&s->pmc.efuse.ctrl);
+ Object *cache = OBJECT(&s->pmc.efuse.cache);
+
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse.ctrl,
+ TYPE_XLNX_VERSAL_EFUSE_CTRL);
+
+ object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse.cache,
+ TYPE_XLNX_VERSAL_EFUSE_CACHE);
+
+ object_initialize_child_with_props(ctrl, "efuse-bits", bits,
+ sizeof(s->pmc.efuse.bits),
+ TYPE_XLNX_EFUSE, &error_abort,
+ "efuse-nr", "3",
+ "efuse-size", "8192",
+ NULL);
+
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
+ versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
+ versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
@@ -416,6 +454,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_rtc(s, pic);
versal_create_xrams(s, pic);
versal_create_bbram(s, pic);
+ versal_create_efuse(s, pic);
versal_map_ddr(s);
versal_unimp(s);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 7719e8c4d2..33b89f00b6 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -25,6 +25,7 @@
#include "hw/usb/xlnx-usb-subsystem.h"
#include "hw/misc/xlnx-versal-xramc.h"
#include "hw/nvram/xlnx-bbram.h"
+#include "hw/nvram/xlnx-versal-efuse.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -81,6 +82,11 @@ struct Versal {
XlnxZynqMPRTC rtc;
XlnxBBRam bbram;
+ struct {
+ XlnxVersalEFuseCtrl ctrl;
+ XlnxVersalEFuseCache cache;
+ XLNXEFuse bits;
+ } efuse;
} pmc;
struct {
@@ -110,6 +116,7 @@ struct Versal {
#define VERSAL_BBRAM_APB_IRQ_0 121
#define VERSAL_RTC_APB_ERR_IRQ 121
#define VERSAL_SD0_IRQ_0 126
+#define VERSAL_EFUSE_IRQ 139
#define VERSAL_RTC_ALARM_IRQ 142
#define VERSAL_RTC_SECONDS_IRQ 143
@@ -175,6 +182,11 @@ struct Versal {
#define MM_PMC_SD0_SIZE 0x10000
#define MM_PMC_BBRAM_CTRL 0xf11f0000
#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
+#define MM_PMC_EFUSE_CTRL 0xf1240000
+#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
+#define MM_PMC_EFUSE_CACHE 0xf1250000
+#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
+
#define MM_PMC_CRP 0xf1260000U
#define MM_PMC_CRP_SIZE 0x10000
#define MM_PMC_RTC 0xf12a0000
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 8/9] hw/arm: xlnx-zynqmp: Add Xilinx BBRAM device
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
` (6 preceding siblings ...)
2021-08-19 4:03 ` [PATCH 7/9] hw/arm: xlnx-versal: Add Xilinx eFUSE device Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 4:03 ` [PATCH 9/9] hw/arm: xlnx-zynqmp: Add Xilinx eFUSE device Tong Ho
2021-08-19 15:08 ` [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Edgar E. Iglesias
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm; +Cc: edgar.iglesias, alistair, tong.ho, qemu-devel, peter.maydell
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/arm/xlnx-zynqmp.c | 21 +++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 3597e8db4d..8e39b7d6c7 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -62,6 +62,9 @@
#define RTC_ADDR 0xffa60000
#define RTC_IRQ 26
+#define BBRAM_ADDR 0xffcd0000
+#define BBRAM_IRQ 11
+
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
@@ -222,6 +225,22 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
}
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
+ sizeof(s->bbram), TYPE_XLNX_BBRAM,
+ &error_fatal,
+ "crc-zpads", "1",
+ NULL);
+ sbd = SYS_BUS_DEVICE(&s->bbram);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -616,6 +635,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
+ xlnx_zynqmp_create_bbram(s, gic_spi);
+
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
errp)) {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index d3e2ef97f6..07ebcefbab 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -36,6 +36,7 @@
#include "qom/object.h"
#include "net/can_emu.h"
#include "hw/dma/xlnx_csu_dma.h"
+#include "hw/nvram/xlnx-bbram.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -95,6 +96,7 @@ struct XlnxZynqMPState {
MemoryRegion *ddr_ram;
MemoryRegion ddr_ram_low, ddr_ram_high;
+ XlnxBBRam bbram;
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 9/9] hw/arm: xlnx-zynqmp: Add Xilinx eFUSE device
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
` (7 preceding siblings ...)
2021-08-19 4:03 ` [PATCH 8/9] hw/arm: xlnx-zynqmp: Add Xilinx BBRAM device Tong Ho
@ 2021-08-19 4:03 ` Tong Ho
2021-08-19 15:08 ` [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Edgar E. Iglesias
9 siblings, 0 replies; 11+ messages in thread
From: Tong Ho @ 2021-08-19 4:03 UTC (permalink / raw)
To: qemu-arm; +Cc: edgar.iglesias, alistair, tong.ho, qemu-devel, peter.maydell
Connect the support for ZynqMP eFUSE one-time field-programmable
bit array.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 32 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 8e39b7d6c7..9e458ad1c0 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -65,6 +65,9 @@
#define BBRAM_ADDR 0xffcd0000
#define BBRAM_IRQ 11
+#define EFUSE_ADDR 0xffcc0000
+#define EFUSE_IRQ 87
+
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
@@ -241,6 +244,31 @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
}
+static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ Object *bits = OBJECT(&s->efuse_bits);
+ Object *ctrl = OBJECT(&s->efuse);
+ SysBusDevice *sbd;
+
+ object_initialize_child(OBJECT(s), "efuse", &s->efuse,
+ TYPE_XLNX_ZYNQMP_EFUSE);
+
+ object_initialize_child_with_props(ctrl, "efuse-bits", bits,
+ sizeof(s->efuse_bits),
+ TYPE_XLNX_EFUSE, &error_abort,
+ "efuse-nr", "3",
+ "efuse-size", "2048",
+ NULL);
+
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
+ object_property_set_link(ctrl, "efuse", bits, &error_abort);
+
+ sbd = SYS_BUS_DEVICE(ctrl);
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -636,6 +664,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
xlnx_zynqmp_create_bbram(s, gic_spi);
+ xlnx_zynqmp_create_efuse(s, gic_spi);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 07ebcefbab..876e8bf4e3 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -37,6 +37,7 @@
#include "net/can_emu.h"
#include "hw/dma/xlnx_csu_dma.h"
#include "hw/nvram/xlnx-bbram.h"
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -97,6 +98,8 @@ struct XlnxZynqMPState {
MemoryRegion *ddr_ram;
MemoryRegion ddr_ram_low, ddr_ram_high;
XlnxBBRam bbram;
+ XlnxZynqMPEFuse efuse;
+ XLNXEFuse efuse_bits;
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM
2021-08-19 4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
` (8 preceding siblings ...)
2021-08-19 4:03 ` [PATCH 9/9] hw/arm: xlnx-zynqmp: Add Xilinx eFUSE device Tong Ho
@ 2021-08-19 15:08 ` Edgar E. Iglesias
9 siblings, 0 replies; 11+ messages in thread
From: Edgar E. Iglesias @ 2021-08-19 15:08 UTC (permalink / raw)
To: Tong Ho; +Cc: peter.maydell, qemu-arm, qemu-devel, alistair
On Wed, Aug 18, 2021 at 09:02:59PM -0700, Tong Ho wrote:
> This series implements the Xilinx eFUSE and BBRAM devices for
> the Versal and ZynqMP product families.
>
> Furthermore, both new devices are connected to the xlnx-versal-virt
> board and the xlnx-zcu102 board.
Hi Tong,
A few general comments.
Patch #1 should probably be moved to be the last patch of the series.
I think we should remove the commands about register generation
"Partially generated by xregqemu.py". It may be confusing to others
since it's not a tool we run in the build process but rather a one
off extraction of reg definitions...
Thanks!
Edgar
^ permalink raw reply [flat|nested] 11+ messages in thread