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From: Tong Ho <tong.ho@xilinx.com>
To: <qemu-arm@nongnu.org>
Cc: edgar.iglesias@gmail.com, alistair@alistair23.me,
	tong.ho@xilinx.com, qemu-devel@nongnu.org,
	peter.maydell@linaro.org
Subject: [PATCH 8/9] hw/arm: xlnx-zynqmp: Add Xilinx BBRAM device
Date: Wed, 18 Aug 2021 21:03:07 -0700	[thread overview]
Message-ID: <20210819040308.675057-9-tong.ho@xilinx.com> (raw)
In-Reply-To: <20210819040308.675057-1-tong.ho@xilinx.com>

Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)

Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
 hw/arm/xlnx-zynqmp.c         | 21 +++++++++++++++++++++
 include/hw/arm/xlnx-zynqmp.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 3597e8db4d..8e39b7d6c7 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -62,6 +62,9 @@
 #define RTC_ADDR            0xffa60000
 #define RTC_IRQ             26
 
+#define BBRAM_ADDR          0xffcd0000
+#define BBRAM_IRQ           11
+
 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
 
 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
@@ -222,6 +225,22 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
     qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
 }
 
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
+{
+    SysBusDevice *sbd;
+
+    object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
+                                       sizeof(s->bbram), TYPE_XLNX_BBRAM,
+                                       &error_fatal,
+                                       "crc-zpads", "1",
+                                       NULL);
+    sbd = SYS_BUS_DEVICE(&s->bbram);
+
+    sysbus_realize(sbd, &error_fatal);
+    sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
+    sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
+}
+
 static void xlnx_zynqmp_init(Object *obj)
 {
     MachineState *ms = MACHINE(qdev_get_machine());
@@ -616,6 +635,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
 
+    xlnx_zynqmp_create_bbram(s, gic_spi);
+
     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
         if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
                                       errp)) {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index d3e2ef97f6..07ebcefbab 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -36,6 +36,7 @@
 #include "qom/object.h"
 #include "net/can_emu.h"
 #include "hw/dma/xlnx_csu_dma.h"
+#include "hw/nvram/xlnx-bbram.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -95,6 +96,7 @@ struct XlnxZynqMPState {
 
     MemoryRegion *ddr_ram;
     MemoryRegion ddr_ram_low, ddr_ram_high;
+    XlnxBBRam bbram;
 
     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
-- 
2.25.1



  parent reply	other threads:[~2021-08-19  4:12 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-19  4:02 [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
2021-08-19  4:03 ` [PATCH 1/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage Tong Ho
2021-08-19  4:03 ` [PATCH 2/9] hw/nvram: Introduce Xilinx eFuse QOM Tong Ho
2021-08-19  4:03 ` [PATCH 3/9] hw/nvram: Introduce Xilinx Versal eFuse device Tong Ho
2021-08-19  4:03 ` [PATCH 4/9] hw/nvram: Introduce Xilinx ZynqMP " Tong Ho
2021-08-19  4:03 ` [PATCH 5/9] hw/nvram: Introduce Xilinx battery-backed ram Tong Ho
2021-08-19  4:03 ` [PATCH 6/9] hw/arm: xlnx-versal: Add Xilinx BBRAM device Tong Ho
2021-08-19  4:03 ` [PATCH 7/9] hw/arm: xlnx-versal: Add Xilinx eFUSE device Tong Ho
2021-08-19  4:03 ` Tong Ho [this message]
2021-08-19  4:03 ` [PATCH 9/9] hw/arm: xlnx-zynqmp: " Tong Ho
2021-08-19 15:08 ` [PATCH 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Edgar E. Iglesias

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