From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v3 14/21] target/riscv: Use {get, dest}_gpr for integer load/store
Date: Wed, 18 Aug 2021 23:04:55 -1000 [thread overview]
Message-ID: <20210819090502.428068-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210819090502.428068-1-richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 36 +++++++++++++------------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index af3e0bc0e6..f616a26c82 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -138,15 +138,17 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(ctx, t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(ctx, a->rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
+ if (a->imm) {
+ TCGv temp = temp_new(ctx);
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
+ gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -177,19 +179,19 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(ctx, t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
- gen_get_gpr(ctx, dat, a->rs2);
+ TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
+ if (a->imm) {
+ TCGv temp = temp_new(ctx);
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
}
-
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
return gen_store(ctx, a, MO_SB);
--
2.25.1
next prev parent reply other threads:[~2021-08-19 9:11 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-19 9:04 [PATCH v3 00/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-19 9:04 ` [PATCH v3 01/21] " Richard Henderson
2021-08-19 9:04 ` [PATCH v3 02/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-19 11:00 ` Bin Meng
2021-08-19 17:23 ` Richard Henderson
2021-08-19 9:04 ` [PATCH v3 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-19 9:04 ` [PATCH v3 04/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-19 11:01 ` Bin Meng
2021-08-19 9:04 ` [PATCH v3 05/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-19 9:04 ` [PATCH v3 06/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-19 9:04 ` [PATCH v3 07/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-19 9:04 ` [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-20 1:35 ` Alistair Francis
2021-08-19 9:04 ` [PATCH v3 09/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-19 9:04 ` [PATCH v3 10/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-19 9:04 ` [PATCH v3 11/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-19 9:04 ` [PATCH v3 12/21] target/riscv: Add gen_greviw Richard Henderson
2021-08-19 9:04 ` [PATCH v3 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-19 9:04 ` Richard Henderson [this message]
2021-08-19 9:04 ` [PATCH v3 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-19 9:04 ` [PATCH v3 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-19 9:04 ` [PATCH v3 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-19 9:04 ` [PATCH v3 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-19 9:05 ` [PATCH v3 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-19 9:05 ` [PATCH v3 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-19 9:05 ` [PATCH v3 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210819090502.428068-15-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=bmeng.cn@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).