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From: Greg Kurz <groug@kaod.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH 05/26] ppc/pnv: Distribute RAM among the chips
Date: Fri, 20 Aug 2021 16:08:49 +0200	[thread overview]
Message-ID: <20210820160849.4ad703b1@bahia.lan> (raw)
In-Reply-To: <20210809134547.689560-6-clg@kaod.org>

On Mon, 9 Aug 2021 15:45:26 +0200
Cédric Le Goater <clg@kaod.org> wrote:

> But always give the first 1GB to chip 0 as skiboot requires it.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/ppc/pnv.c | 33 +++++++++++++++++++++++++--------
>  1 file changed, 25 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 025f01c55744..2f5358b70c95 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -710,6 +710,23 @@ static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
>      pnv_psi_pic_print_info(&chip10->psi, mon);
>  }
>  
> +/* Always give the first 1GB to chip 0 else we won't boot */
> +static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
> +{
> +    MachineState *machine = MACHINE(pnv);
> +    uint64_t ram_per_chip;
> +
> +    assert(machine->ram_size >= 1 * GiB);
> +
> +    ram_per_chip = machine->ram_size / pnv->num_chips;
> +    if (ram_per_chip >= 1 * GiB) {
> +        return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
> +    }
> +

So this is only reached if pnv->num_chips is >= 2, since
a single chip would have ram_per_chip == machine->ram_size
and thus take the return branch above.

Maybe worth making it clear with an assert() ?

> +    ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);

Suggesting that because I was looking for a potential divide by zero ^^

> +    return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
> +}
> +
>  static void pnv_init(MachineState *machine)
>  {
>      const char *bios_name = machine->firmware ?: FW_FILE_NAME;
> @@ -717,6 +734,7 @@ static void pnv_init(MachineState *machine)
>      MachineClass *mc = MACHINE_GET_CLASS(machine);
>      char *fw_filename;
>      long fw_size;
> +    uint64_t chip_ram_start = 0;
>      int i;
>      char *chip_typename;
>      DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
> @@ -821,17 +839,16 @@ static void pnv_init(MachineState *machine)
>          char chip_name[32];
>          Object *chip = OBJECT(qdev_new(chip_typename));
>          int chip_id = i;
> +        uint64_t chip_ram_size =  pnv_chip_get_ram_size(pnv, chip_id);
>  
>          pnv->chips[i] = PNV_CHIP(chip);
>  
> -        /*
> -         * TODO: put all the memory in one node on chip 0 until we find a
> -         * way to specify different ranges for each chip
> -         */
> -        if (i == 0) {
> -            object_property_set_int(chip, "ram-size", machine->ram_size,
> -                                    &error_fatal);
> -        }
> +        /* Distribute RAM among the chips  */
> +        object_property_set_int(chip, "ram-start", chip_ram_start,
> +                                &error_fatal);
> +        object_property_set_int(chip, "ram-size", chip_ram_size,
> +                                &error_fatal);

Not really related but failing to set either of these looks
like it should never happen so I'd rather pass &error_abort
for debugging purpose.

Anyway,

Reviewed-by: Greg Kurz <groug@kaod.org>

> +        chip_ram_start += chip_ram_size;
>  
>          snprintf(chip_name, sizeof(chip_name), "chip[%d]", chip_id);
>          object_property_add_child(OBJECT(pnv), chip_name, chip);



  reply	other threads:[~2021-08-20 14:10 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-09 13:45 [PATCH 00/26] ppc/pnv: Extend the powernv10 machine Cédric Le Goater
2021-08-09 13:45 ` [PATCH 01/26] ppc: Add a POWER10 DD2 CPU Cédric Le Goater
2021-08-20 13:40   ` Greg Kurz
2021-08-30  7:10     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 02/26] ppc/pnv: Change the POWER10 machine to support DD2 only Cédric Le Goater
2021-08-20 13:41   ` Greg Kurz
2021-08-09 13:45 ` [PATCH 03/26] ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode Cédric Le Goater
2021-08-09 13:45 ` [PATCH 04/26] ppc/pnv: Use a simple incrementing index for the chip-id Cédric Le Goater
2021-08-20 13:51   ` Greg Kurz
2021-08-30  7:11     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 05/26] ppc/pnv: Distribute RAM among the chips Cédric Le Goater
2021-08-20 14:08   ` Greg Kurz [this message]
2021-08-30  7:14     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 06/26] ppc/pnv: add a chip topology index for POWER10 Cédric Le Goater
2021-08-20 14:12   ` Greg Kurz
2021-08-30  7:15     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 07/26] ppc/xive: Export PQ get/set routines Cédric Le Goater
2021-08-09 13:45 ` [PATCH 08/26] ppc/xive: Export xive_presenter_notify() Cédric Le Goater
2021-08-09 13:45 ` [PATCH 09/26] ppc/xive2: Introduce a XIVE2 core framework Cédric Le Goater
2021-08-10  6:06   ` David Gibson
2021-08-10 13:04     ` Cédric Le Goater
2021-08-23 15:15   ` Greg Kurz
2021-08-30  7:17     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 10/26] ppc/xive2: Introduce a presenter matching routine Cédric Le Goater
2021-08-25  6:01   ` David Gibson
2021-08-30  7:15     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 11/26] ppc/pnv: Add a XIVE2 controller to the POWER10 chip Cédric Le Goater
2021-08-09 13:45 ` [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10 Cédric Le Goater
2021-08-25  6:06   ` David Gibson
2021-08-09 13:45 ` [PATCH 13/26] ppc/pnv: Add POWER10 quads Cédric Le Goater
2021-08-25  6:09   ` David Gibson
2021-08-31 13:45     ` Cédric Le Goater
2021-08-09 13:45 ` [PATCH 14/26] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge Cédric Le Goater
2021-08-09 13:45 ` [PATCH 15/26] ppc/pnv: Add a HOMER model to POWER10 Cédric Le Goater
2021-08-25  6:12   ` David Gibson
2021-08-09 13:45 ` [PATCH 16/26] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) Cédric Le Goater
2021-08-09 13:45 ` [PATCH 17/26] ppc/xive2: Add support for notification injection on ESB pages Cédric Le Goater
2021-08-09 13:45 ` [PATCH 18/26] ppc/xive: Add support for PQ state bits offload Cédric Le Goater
2021-08-09 13:45 ` [PATCH 19/26] ppc/pnv: Add support for PQ offload on PHB5 Cédric Le Goater
2021-08-09 13:45 ` [PATCH 20/26] ppc/pnv: Add support for PHB5 "Address-based trigger" mode Cédric Le Goater
2021-08-09 13:45 ` [PATCH 21/26] pnv/xive2: Introduce new capability bits Cédric Le Goater
2021-08-09 13:45 ` [PATCH 22/26] ppc/pnv: add XIVE Gen2 TIMA support Cédric Le Goater
2021-08-09 13:45 ` [PATCH 23/26] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) Cédric Le Goater
2021-08-09 13:45 ` [PATCH 24/26] xive2: Add a get_config() handler for the router configuration Cédric Le Goater
2021-08-09 13:45 ` [PATCH 25/26] pnv/xive2: Add support for automatic save&restore Cédric Le Goater
2021-08-09 13:45 ` [PATCH 26/26] pnv/xive2: Add support for 8bits thread id Cédric Le Goater
2021-08-10  3:07 ` [PATCH 00/26] ppc/pnv: Extend the powernv10 machine David Gibson
2021-08-10  3:12 ` David Gibson
2021-08-10  8:58   ` Cédric Le Goater

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