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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id e26sm13804358pfj.46.2021.08.22.19.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Aug 2021 19:08:21 -0700 (PDT) From: Bin Meng To: Damien Hedde , "Edgar E . Iglesias" , Alistair Francis , Peter Maydell Subject: [PATCH 0/3] hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure Date: Mon, 23 Aug 2021 10:08:10 +0800 Message-Id: <20210823020813.25192-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" As of today, when booting upstream U-Boot for Xilinx Zynq, the UART does not receive anything. Debugging shows that the UART input clock frequency is zero which prevents the UART from receiving anything as. per the logic in uart_receive(). Note the U-Boot can still output data to the UART tx fifo, which should not happen, as the design seems to prevent the data transmission when clock is not enabled but somehow it only applies to the Rx side. For anyone who is interested to give a try, here is the U-Boot defconfig: $ make xilinx_zynq_virt_defconfig and QEMU commands to test U-Boot: $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \ -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0 Note U-Boot used to boot properly in QEMU 4.2.0 which is the QEMU version used in current U-Boot's CI testing. The UART clock changes were introduced by the following 3 commits: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts") b636db306e06 ("hw/char/cadence_uart: add clock support") 5b49a34c6800 ("hw/arm/xilinx_zynq: connect uart clocks to slcr") Bin Meng (3): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char/cadence_uart.c | 16 +++++++++++----- hw/misc/zynq_slcr.c | 31 ++++++++++++++++++------------- 2 files changed, 29 insertions(+), 18 deletions(-) -- 2.25.1