From: Bin Meng <bmeng.cn@gmail.com>
To: Damien Hedde <damien.hedde@greensocs.com>,
"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
Alistair Francis <alistair.francis@wdc.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 3/3] hw/char: cadence_uart: Move clock/reset check to uart_can_receive()
Date: Mon, 23 Aug 2021 10:08:13 +0800 [thread overview]
Message-ID: <20210823020813.25192-4-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210823020813.25192-1-bmeng.cn@gmail.com>
Currently the clock/reset check is done in uart_receive(), but we
can move the check to uart_can_receive() which is earlier.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/char/cadence_uart.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 154be34992..7326445385 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -235,6 +235,12 @@ static void uart_parameters_setup(CadenceUARTState *s)
static int uart_can_receive(void *opaque)
{
CadenceUARTState *s = opaque;
+
+ /* ignore characters when unclocked or in reset */
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+ return 0;
+ }
+
int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
@@ -358,11 +364,6 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
CadenceUARTState *s = opaque;
uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
- /* ignore characters when unclocked or in reset */
- if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
- return;
- }
-
if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
uart_write_rx_fifo(opaque, buf, size);
}
--
2.25.1
next prev parent reply other threads:[~2021-08-23 2:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 2:08 [PATCH 0/3] hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure Bin Meng
2021-08-23 2:08 ` [PATCH 1/3] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase Bin Meng
2021-08-23 4:42 ` Alistair Francis
2021-08-23 13:45 ` Edgar E. Iglesias
2021-08-23 2:08 ` [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled Bin Meng
2021-08-23 4:43 ` Alistair Francis
2021-08-23 4:52 ` Bin Meng
2021-08-23 6:52 ` Alistair Francis
2021-08-23 13:58 ` Edgar E. Iglesias
2021-08-23 8:14 ` Philippe Mathieu-Daudé
2021-08-23 9:57 ` Bin Meng
2021-08-23 10:43 ` Philippe Mathieu-Daudé
2021-08-23 13:14 ` Bin Meng
2021-08-23 13:21 ` Philippe Mathieu-Daudé
2021-08-23 2:08 ` Bin Meng [this message]
2021-08-23 8:17 ` [PATCH 3/3] hw/char: cadence_uart: Move clock/reset check to uart_can_receive() Philippe Mathieu-Daudé
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