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[31.30.174.132]) by smtp.gmail.com with ESMTPSA id n23sm9755721eds.41.2021.08.23.08.53.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 08:53:21 -0700 (PDT) Date: Mon, 23 Aug 2021 17:53:20 +0200 From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: Re: [PATCH 0/4] target/arm/cpu: Introduce sve_vq_supported bitmap Message-ID: <20210823155320.6pr3432lzoihn32a@gator.home> References: <20210819193758.149660-1-drjones@redhat.com> MIME-Version: 1.0 In-Reply-To: <20210819193758.149660-1-drjones@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.743, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, ishii.shuuichir@fujitsu.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Aug 19, 2021 at 09:37:54PM +0200, Andrew Jones wrote: > While reviewing the new A64FX CPU type it became clear that CPU > types should be able to specify which SVE vector lengths are > supported. This series adds a new bitmap member to ARMCPU and > modifies arm_cpu_sve_finalize() to validate inputs against it. > So far we only need to set the bitmap for the 'max' CPU type > though and, since it supports all vector lengths, we just fill > the whole thing. > > This series was inspired by Richard Henderson's suggestion to > replace arm_cpu_sve_finalize's kvm_supported bitmap with something > that could be shared with TCG. > > So far I've only lightly tested this. I'll do more testing and > report back later. I'd also be happy to get test results from > others. I did more testing and it looks good to me except for the extra space in an error message that I reported in patch 4. Thanks, drew > > Thanks, > drew > > Andrew Jones (4): > target/arm/cpu: Introduce sve_vq_supported bitmap > target/arm/kvm64: Ensure sve vls map is completely clear > target/arm/cpu64: Replace kvm_supported with sve_vq_supported > target/arm/cpu64: Validate sve vector lengths are supported > > target/arm/cpu.h | 4 ++ > target/arm/cpu64.c | 118 +++++++++++++++++++++------------------------ > target/arm/kvm64.c | 2 +- > 3 files changed, 61 insertions(+), 63 deletions(-) > > -- > 2.31.1 >