From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"David Hildenbrand" <david@redhat.com>,
"Jason Wang" <jasowang@redhat.com>, "Li Qiang" <liq3ea@gmail.com>,
"Qiuhao Li" <Qiuhao.Li@outlook.com>,
"Peter Xu" <peterx@redhat.com>,
"Alexander Bulekov" <alxndr@bu.edu>,
qemu-arm@nongnu.org, "Gerd Hoffmann" <kraxel@redhat.com>,
"Stefan Hajnoczi" <stefanha@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [RFC PATCH v2 3/5] exec/memattrs: Introduce MemTxAttrs::bus_perm field
Date: Mon, 23 Aug 2021 18:41:55 +0200 [thread overview]
Message-ID: <20210823164157.751807-4-philmd@redhat.com> (raw)
In-Reply-To: <20210823164157.751807-1-philmd@redhat.com>
Add the 'direct_access' bit to the memory attributes to restrict
bus master access to ROM/RAM.
Have read/write accessors return MEMTX_BUS_ERROR if an access is
restricted and the region is not ROM/RAM ('direct').
Add corresponding trace events.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/exec/memattrs.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 95f2d20d55b..7a94ee75a88 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -14,6 +14,13 @@
#ifndef MEMATTRS_H
#define MEMATTRS_H
+/* Permission to restrict bus memory accesses. See MemTxAttrs::bus_perm */
+enum {
+ MEMTXPERM_UNSPECIFIED = 0,
+ MEMTXPERM_UNRESTRICTED = 1,
+ MEMTXPERM_RAM_DEVICE = 2,
+};
+
/* Every memory transaction has associated with it a set of
* attributes. Some of these are generic (such as the ID of
* the bus master); some are specific to a particular kind of
@@ -35,6 +42,19 @@ typedef struct MemTxAttrs {
unsigned int secure:1;
/* Memory access is usermode (unprivileged) */
unsigned int user:1;
+ /*
+ * Bus memory access permission.
+ *
+ * Some devices (such DMA) might be restricted to only access
+ * some type of device, such RAM devices. By default memory
+ * accesses are unspecified (MEMTXPERM_UNSPECIFIED), but could be
+ * unrestricted (MEMTXPERM_UNRESTRICTED, similar to an allow list)
+ * or restricted to a type of devices (similar to a deny list).
+ * Currently only RAM devices can be restricted (MEMTXPERM_RAM_DEVICE).
+ *
+ * Memory accesses to restricted addresses return MEMTX_BUS_ERROR.
+ */
+ unsigned int bus_perm:2;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
/* Invert endianness for this page */
@@ -66,6 +86,7 @@ typedef struct MemTxAttrs {
#define MEMTX_OK 0
#define MEMTX_ERROR (1U << 0) /* device returned an error */
#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
+#define MEMTX_BUS_ERROR (1U << 2) /* bus returned an error */
typedef uint32_t MemTxResult;
#endif
--
2.31.1
next prev parent reply other threads:[~2021-08-23 16:58 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 16:41 [RFC PATCH v2 0/5] physmem: Have flaview API check bus permission from MemTxAttrs argument Philippe Mathieu-Daudé
2021-08-23 16:41 ` [RFC PATCH v2 1/5] softmmu/physmem: Simplify flatview_write and address_space_access_valid Philippe Mathieu-Daudé
2021-08-23 18:45 ` Peter Xu
2021-08-23 18:59 ` David Hildenbrand
2021-08-24 9:03 ` Alexander Bulekov
2021-08-24 13:04 ` Stefan Hajnoczi
2021-08-23 16:41 ` [RFC PATCH v2 2/5] hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR Philippe Mathieu-Daudé
2021-08-23 18:46 ` Peter Xu
2021-08-23 19:01 ` David Hildenbrand
2021-08-23 19:07 ` Peter Maydell
2021-08-24 13:04 ` Stefan Hajnoczi
2021-08-23 16:41 ` Philippe Mathieu-Daudé [this message]
2021-08-23 18:41 ` [RFC PATCH v2 3/5] exec/memattrs: Introduce MemTxAttrs::bus_perm field Peter Xu
2021-08-23 19:04 ` David Hildenbrand
2021-12-15 17:14 ` Philippe Mathieu-Daudé
2021-08-24 13:08 ` Stefan Hajnoczi
2021-12-15 17:11 ` Philippe Mathieu-Daudé
2021-08-23 16:41 ` [RFC PATCH v2 4/5] softmmu/physmem: Introduce flatview_access_allowed() to check bus perms Philippe Mathieu-Daudé
2021-08-23 18:43 ` Peter Xu
2021-08-23 19:03 ` David Hildenbrand
2021-08-24 13:13 ` Stefan Hajnoczi
2021-08-23 16:41 ` [RFC PATCH v2 5/5] softmmu/physmem: Have flaview API check MemTxAttrs::bus_perm field Philippe Mathieu-Daudé
2021-08-23 18:45 ` Peter Xu
2021-08-23 19:10 ` David Hildenbrand
2021-08-24 13:15 ` Stefan Hajnoczi
2021-08-24 13:50 ` Philippe Mathieu-Daudé
2021-08-24 14:21 ` Peter Maydell
2021-11-18 21:04 ` Philippe Mathieu-Daudé
2021-08-23 19:10 ` [RFC PATCH v2 0/5] physmem: Have flaview API check bus permission from MemTxAttrs argument Peter Maydell
2021-08-23 20:50 ` Peter Xu
2021-08-23 22:26 ` Alexander Bulekov
2021-08-24 7:24 ` Philippe Mathieu-Daudé
2021-08-24 9:49 ` Peter Maydell
2021-08-24 12:01 ` Gerd Hoffmann
2021-08-24 12:12 ` Li Qiang
2021-08-24 19:34 ` Peter Xu
2021-08-24 9:25 ` Edgar E. Iglesias
2021-08-24 13:26 ` Stefan Hajnoczi
2021-08-24 8:58 ` Stefan Hajnoczi
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