From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v5 02/24] tests/tcg/riscv64: Add test for division
Date: Mon, 23 Aug 2021 12:55:07 -0700 [thread overview]
Message-ID: <20210823195529.560295-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210823195529.560295-1-richard.henderson@linaro.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/riscv64/test-div.c | 58 +++++++++++++++++++++++++++++++
tests/tcg/riscv64/Makefile.target | 5 +++
2 files changed, 63 insertions(+)
create mode 100644 tests/tcg/riscv64/test-div.c
create mode 100644 tests/tcg/riscv64/Makefile.target
diff --git a/tests/tcg/riscv64/test-div.c b/tests/tcg/riscv64/test-div.c
new file mode 100644
index 0000000000..a90480be3f
--- /dev/null
+++ b/tests/tcg/riscv64/test-div.c
@@ -0,0 +1,58 @@
+#include <assert.h>
+#include <limits.h>
+
+struct TestS {
+ long x, y, q, r;
+};
+
+static struct TestS test_s[] = {
+ { 4, 2, 2, 0 }, /* normal cases */
+ { 9, 7, 1, 2 },
+ { 0, 0, -1, 0 }, /* div by zero cases */
+ { 9, 0, -1, 9 },
+ { LONG_MIN, -1, LONG_MIN, 0 }, /* overflow case */
+};
+
+struct TestU {
+ unsigned long x, y, q, r;
+};
+
+static struct TestU test_u[] = {
+ { 4, 2, 2, 0 }, /* normal cases */
+ { 9, 7, 1, 2 },
+ { 0, 0, ULONG_MAX, 0 }, /* div by zero cases */
+ { 9, 0, ULONG_MAX, 9 },
+};
+
+#define ARRAY_SIZE(X) (sizeof(X) / sizeof(*(X)))
+
+int main (void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(test_s); i++) {
+ long q, r;
+
+ asm("div %0, %2, %3\n\t"
+ "rem %1, %2, %3"
+ : "=&r" (q), "=r" (r)
+ : "r" (test_s[i].x), "r" (test_s[i].y));
+
+ assert(q == test_s[i].q);
+ assert(r == test_s[i].r);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(test_u); i++) {
+ unsigned long q, r;
+
+ asm("divu %0, %2, %3\n\t"
+ "remu %1, %2, %3"
+ : "=&r" (q), "=r" (r)
+ : "r" (test_u[i].x), "r" (test_u[i].y));
+
+ assert(q == test_u[i].q);
+ assert(r == test_u[i].r);
+ }
+
+ return 0;
+}
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
new file mode 100644
index 0000000000..d41bf6d60d
--- /dev/null
+++ b/tests/tcg/riscv64/Makefile.target
@@ -0,0 +1,5 @@
+# -*- Mode: makefile -*-
+# RISC-V specific tweaks
+
+VPATH += $(SRC_PATH)/tests/tcg/riscv64
+TESTS += test-div
--
2.25.1
next prev parent reply other threads:[~2021-08-23 19:59 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 19:55 [PATCH v5 00/24] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-23 19:55 ` [PATCH v5 01/24] " Richard Henderson
2021-08-23 19:55 ` Richard Henderson [this message]
2021-08-23 19:55 ` [PATCH v5 03/24] target/riscv: Clean up division helpers Richard Henderson
2021-08-23 19:55 ` [PATCH v5 04/24] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-23 19:55 ` [PATCH v5 05/24] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-23 19:55 ` [PATCH v5 06/24] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-23 19:55 ` [PATCH v5 07/24] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-23 19:55 ` [PATCH v5 08/24] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-23 19:55 ` [PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-23 19:55 ` [PATCH v5 10/24] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-23 19:55 ` [PATCH v5 11/24] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-23 19:55 ` [PATCH v5 12/24] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-23 19:55 ` [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw Richard Henderson
2021-08-24 7:23 ` Bin Meng
2021-08-25 6:07 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 14/24] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-23 19:55 ` [PATCH v5 15/24] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-23 19:55 ` [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation Richard Henderson
2021-08-24 6:37 ` Bin Meng
2021-08-25 6:08 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 17/24] target/riscv: Fix hgeie, hgeip Richard Henderson
2021-08-24 6:38 ` Bin Meng
2021-08-25 6:09 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 18/24] target/riscv: Reorg csr instructions Richard Henderson
2021-08-25 6:03 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 19/24] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-25 6:06 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-25 6:11 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-25 6:17 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-25 6:19 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 23/24] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-30 4:54 ` Alistair Francis
2021-08-23 19:55 ` [PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
2021-08-30 4:56 ` Alistair Francis
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