From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/37] target/arm/cpu: Introduce sve_vq_supported bitmap
Date: Thu, 26 Aug 2021 18:02:36 +0100 [thread overview]
Message-ID: <20210826170307.27733-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210826170307.27733-1-peter.maydell@linaro.org>
From: Andrew Jones <drjones@redhat.com>
Allow CPUs that support SVE to specify which SVE vector lengths they
support by setting them in this bitmap. Currently only the 'max' and
'host' CPU types supports SVE and 'host' requires KVM which obtains
its supported bitmap from the host. So, we only need to initialize the
bitmap for 'max' with TCG. And, since 'max' should support all SVE
vector lengths we simply fill the bitmap. Future CPU types may have
less trivial maps though.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823160647.34028-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 ++++
target/arm/cpu64.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5cf8996ae3c..1060825c746 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1020,9 +1020,13 @@ struct ARMCPU {
* While processing properties during initialization, corresponding
* sve_vq_init bits are set for bits in sve_vq_map that have been
* set by properties.
+ *
+ * Bits set in sve_vq_supported represent valid vector lengths for
+ * the CPU type.
*/
DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
+ DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ);
/* Generic timer counter frequency, in Hz */
uint64_t gt_cntfrq_hz;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c690318a9b6..eb9318c83b7 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -840,6 +840,8 @@ static void aarch64_max_initfn(Object *obj)
/* Default to PAUTH on, with the architected algorithm. */
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
+
+ bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
}
aarch64_add_sve_properties(obj);
--
2.20.1
next prev parent reply other threads:[~2021-08-26 17:11 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-26 17:02 [PULL 00/37] target-arm queue Peter Maydell
2021-08-26 17:02 ` [PULL 01/37] hw/arm/xlnx-zynqmp: Realize qspi controller *after* qspi_dma Peter Maydell
2021-08-26 17:02 ` [PULL 02/37] hw/dma/xlnx_csu_dma: Run trivial checks early in realize() Peter Maydell
2021-08-26 17:02 ` [PULL 03/37] hw/dma/xlnx_csu_dma: Always expect 'dma' link property to be set Peter Maydell
2021-08-26 17:02 ` [PULL 04/37] hw/dma/xlnx-zdma " Peter Maydell
2021-08-26 17:02 ` [PULL 05/37] hw/arm/Kconfig: no need to enable ACPI_MEMORY_HOTPLUG/ACPI_NVDIMM explicitly Peter Maydell
2021-08-26 17:02 ` Peter Maydell [this message]
2021-08-26 17:02 ` [PULL 07/37] target/arm/kvm64: Ensure sve vls map is completely clear Peter Maydell
2021-08-26 17:02 ` [PULL 08/37] target/arm/cpu64: Replace kvm_supported with sve_vq_supported Peter Maydell
2021-08-26 17:02 ` [PULL 09/37] target/arm/cpu64: Validate sve vector lengths are supported Peter Maydell
2021-08-26 17:02 ` [PULL 10/37] docs/specs/acpu_cpu_hotplug: Convert to rST Peter Maydell
2021-08-26 17:02 ` [PULL 11/37] docs/specs/acpi_mem_hotplug: " Peter Maydell
2021-08-26 17:02 ` [PULL 12/37] docs/specs/acpi_pci_hotplug: " Peter Maydell
2021-08-26 17:02 ` [PULL 13/37] docs/specs/acpi_nvdimm: " Peter Maydell
2021-08-26 17:02 ` [PULL 14/37] MAINTAINERS: Add ACPI specs documents to ACPI and NVDIMM sections Peter Maydell
2021-08-26 17:02 ` [PULL 15/37] softmmu: Use accel_find("xen") instead of xen_available() Peter Maydell
2021-08-26 17:02 ` [PULL 16/37] monitor: Use accel_find("kvm") instead of kvm_available() Peter Maydell
2021-08-26 17:02 ` [PULL 17/37] softmmu/arch_init.c: Trim down include list Peter Maydell
2021-08-26 17:02 ` [PULL 18/37] meson.build: Define QEMU_ARCH in config-target.h Peter Maydell
2021-08-26 17:02 ` [PULL 19/37] arch_init.h: Add QEMU_ARCH_HEXAGON Peter Maydell
2021-08-26 17:02 ` [PULL 20/37] arch_init.h: Move QEMU_ARCH_VIRTIO_* to qdev-monitor.c Peter Maydell
2021-08-26 17:02 ` [PULL 21/37] arch_init.h: Don't include arch_init.h unnecessarily Peter Maydell
2021-08-26 17:02 ` [PULL 22/37] stubs: Remove unused arch_type.c stub Peter Maydell
2021-08-26 17:02 ` [PULL 23/37] hw/core/loader: In gunzip(), check index is in range before use, not after Peter Maydell
2021-08-26 17:02 ` [PULL 24/37] softmmu/physmem.c: Remove unneeded NULL check in qemu_ram_alloc_from_fd() Peter Maydell
2021-08-26 17:02 ` [PULL 25/37] softmmu/physmem.c: Check return value from realpath() Peter Maydell
2021-08-26 17:02 ` [PULL 26/37] net: Zero sockaddr_in in parse_host_port() Peter Maydell
2021-08-26 17:02 ` [PULL 27/37] gdbstub: Zero-initialize sockaddr structs Peter Maydell
2021-08-26 17:02 ` [PULL 28/37] tests/qtest/ipmi-bt-test: Zero-initialize sockaddr struct Peter Maydell
2021-08-26 17:02 ` [PULL 29/37] tests/tcg/multiarch/linux-test: Zero-initialize sockaddr structs Peter Maydell
2021-08-26 17:03 ` [PULL 30/37] raspi: Use error_fatal for SoC realize errors, not error_abort Peter Maydell
2021-08-26 17:03 ` [PULL 31/37] target/arm: Avoid assertion trying to use KVM and multiple ASes Peter Maydell
2021-08-26 17:03 ` [PULL 32/37] hw/arm/virt: Delete EL3 error checksnow provided in CPU realize Peter Maydell
2021-08-26 17:03 ` [PULL 33/37] target/arm: Implement HSTR.TTEE Peter Maydell
2021-08-26 17:03 ` [PULL 34/37] target/arm: Implement HSTR.TJDBX Peter Maydell
2021-08-26 17:03 ` [PULL 35/37] target/arm: Do hflags rebuild in cpsr_write() Peter Maydell
2021-08-26 17:18 ` Philippe Mathieu-Daudé
2021-08-26 17:03 ` [PULL 36/37] hw/arm/xlnx-versal: Add unimplemented APU mmio Peter Maydell
2021-08-26 17:03 ` [PULL 37/37] hw/arm/xlnx-zynqmp: " Peter Maydell
2021-08-26 19:44 ` [PULL 00/37] target-arm queue Peter Maydell
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