From: Andrew Jones <drjones@redhat.com>
To: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX
Date: Tue, 31 Aug 2021 12:20:02 +0200 [thread overview]
Message-ID: <20210831102002.baj3yipk7ulvi32i@gator.home> (raw)
In-Reply-To: <20210831082940.2811719-2-ishii.shuuichir@fujitsu.com>
On Tue, Aug 31, 2021 at 05:29:38PM +0900, Shuuichirou Ishii wrote:
> Add a definition for the Fujitsu A64FX processor.
>
> The A64FX processor does not implement the AArch32 Execution state,
> so there are no associated AArch32 Identification registers.
>
> For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths.
>
> The Identification registers value are defined based on the FX700,
> and have been tested and confirmed.
>
> Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> ---
> target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
I already gave my r-b on the last posting, but here it is again
Reviewed-by: Andrew Jones <drjones@redhat.com>
next prev parent reply other threads:[~2021-08-31 10:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-31 8:29 [PATCH v6 0/3] Add support for Fujitsu A64FX processor Shuuichirou Ishii
2021-08-31 8:29 ` [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX Shuuichirou Ishii
2021-08-31 10:20 ` Andrew Jones [this message]
2021-09-01 6:31 ` ishii.shuuichir
2021-08-31 8:29 ` [PATCH v6 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Shuuichirou Ishii
2021-08-31 8:29 ` [PATCH v6 3/3] tests/arm-cpu-features: Add A64FX processor related Shuuichirou Ishii
2021-09-01 8:23 ` [PATCH v6 0/3] Add support for Fujitsu A64FX processor Peter Maydell
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