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charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The following changes since commit d52dff5d8048d4982437db9606c27bb4127cf9= d0: Merge remote-tracking branch 'remotes/marcandre/tags/clip-pull-request'= into staging (2021-08-31 14:38:15 +0100) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210901-2 for you to fetch changes up to 8e034ae44dba6291beb07f7f2a932c1e5ab83e98: target/riscv: Use {get,dest}_gpr for RVV (2021-09-01 11:59:12 +1000) ---------------------------------------------------------------- First RISC-V PR for QEMU 6.2 - Add a config for Shakti UART - Fixup virt flash node - Don't override users supplied ISA version - Fixup some CSR accesses - Use g_strjoinv() for virt machine PLIC string config - Fix an overflow in the SiFive CLINT - Add 64-bit register access helpers - Replace tcg_const_* with direct constant usage ---------------------------------------------------------------- Bin Meng (2): hw/riscv: virt: Move flash node to root target/riscv: Correct a comment in riscv_csrrw() David Hoppenbrouwers (1): hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_t= imecmp() Joe Komlodi (2): hw/core/register: Add more 64-bit utilities hw/registerfields: Use 64-bit bitfield for FIELD_DP64 LIU Zhiwei (2): target/riscv: Don't wrongly override isa version target/riscv: Add User CSRs read-only check Peter Maydell (1): hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv() Richard Henderson (24): target/riscv: Use tcg_constant_* tests/tcg/riscv64: Add test for division target/riscv: Clean up division helpers target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr target/riscv: Introduce DisasExtend and new helpers target/riscv: Add DisasExtend to gen_arith* target/riscv: Remove gen_arith_div* target/riscv: Use gen_arith for mulh and mulhu target/riscv: Move gen_* helpers for RVM target/riscv: Move gen_* helpers for RVB target/riscv: Add DisasExtend to gen_unary target/riscv: Use DisasExtend in shift operations target/riscv: Use extracts for sraiw and srliw target/riscv: Use get_gpr in branches target/riscv: Use {get, dest}_gpr for integer load/store target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operati= on target/riscv: Fix hgeie, hgeip target/riscv: Reorg csr instructions target/riscv: Use {get,dest}_gpr for RVA target/riscv: Use gen_shift_imm_fn for slli_uw target/riscv: Use {get,dest}_gpr for RVF target/riscv: Use {get,dest}_gpr for RVD target/riscv: Tidy trans_rvh.c.inc target/riscv: Use {get,dest}_gpr for RVV Vijai Kumar K (1): hw/char: Add config for shakti uart include/hw/register.h | 8 + include/hw/registerfields.h | 10 +- target/riscv/helper.h | 6 +- target/riscv/insn32.decode | 1 + hw/core/register.c | 12 + hw/intc/sifive_clint.c | 25 +- hw/riscv/virt.c | 35 +- target/riscv/cpu.c | 14 +- target/riscv/csr.c | 59 ++- target/riscv/op_helper.c | 18 +- target/riscv/translate.c | 689 +++++++-------------------= ------ tests/tcg/riscv64/test-div.c | 58 +++ target/riscv/insn_trans/trans_rva.c.inc | 49 +-- target/riscv/insn_trans/trans_rvb.c.inc | 366 +++++++++++++---- target/riscv/insn_trans/trans_rvd.c.inc | 127 +++--- target/riscv/insn_trans/trans_rvf.c.inc | 149 ++++--- target/riscv/insn_trans/trans_rvh.c.inc | 266 +++--------- target/riscv/insn_trans/trans_rvi.c.inc | 372 +++++++++-------- target/riscv/insn_trans/trans_rvm.c.inc | 193 +++++++-- target/riscv/insn_trans/trans_rvv.c.inc | 149 +++---- hw/char/Kconfig | 3 + hw/char/meson.build | 2 +- hw/riscv/Kconfig | 5 +- tests/tcg/riscv64/Makefile.target | 5 + 24 files changed, 1240 insertions(+), 1381 deletions(-) create mode 100644 tests/tcg/riscv64/test-div.c create mode 100644 tests/tcg/riscv64/Makefile.target