From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 11/33] tests/tcg/riscv64: Add test for division
Date: Wed, 1 Sep 2021 12:09:36 +1000 [thread overview]
Message-ID: <20210901020958.458454-12-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/tcg/riscv64/test-div.c | 58 +++++++++++++++++++++++++++++++
tests/tcg/riscv64/Makefile.target | 5 +++
2 files changed, 63 insertions(+)
create mode 100644 tests/tcg/riscv64/test-div.c
create mode 100644 tests/tcg/riscv64/Makefile.target
diff --git a/tests/tcg/riscv64/test-div.c b/tests/tcg/riscv64/test-div.c
new file mode 100644
index 0000000000..a90480be3f
--- /dev/null
+++ b/tests/tcg/riscv64/test-div.c
@@ -0,0 +1,58 @@
+#include <assert.h>
+#include <limits.h>
+
+struct TestS {
+ long x, y, q, r;
+};
+
+static struct TestS test_s[] = {
+ { 4, 2, 2, 0 }, /* normal cases */
+ { 9, 7, 1, 2 },
+ { 0, 0, -1, 0 }, /* div by zero cases */
+ { 9, 0, -1, 9 },
+ { LONG_MIN, -1, LONG_MIN, 0 }, /* overflow case */
+};
+
+struct TestU {
+ unsigned long x, y, q, r;
+};
+
+static struct TestU test_u[] = {
+ { 4, 2, 2, 0 }, /* normal cases */
+ { 9, 7, 1, 2 },
+ { 0, 0, ULONG_MAX, 0 }, /* div by zero cases */
+ { 9, 0, ULONG_MAX, 9 },
+};
+
+#define ARRAY_SIZE(X) (sizeof(X) / sizeof(*(X)))
+
+int main (void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(test_s); i++) {
+ long q, r;
+
+ asm("div %0, %2, %3\n\t"
+ "rem %1, %2, %3"
+ : "=&r" (q), "=r" (r)
+ : "r" (test_s[i].x), "r" (test_s[i].y));
+
+ assert(q == test_s[i].q);
+ assert(r == test_s[i].r);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(test_u); i++) {
+ unsigned long q, r;
+
+ asm("divu %0, %2, %3\n\t"
+ "remu %1, %2, %3"
+ : "=&r" (q), "=r" (r)
+ : "r" (test_u[i].x), "r" (test_u[i].y));
+
+ assert(q == test_u[i].q);
+ assert(r == test_u[i].r);
+ }
+
+ return 0;
+}
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
new file mode 100644
index 0000000000..d41bf6d60d
--- /dev/null
+++ b/tests/tcg/riscv64/Makefile.target
@@ -0,0 +1,5 @@
+# -*- Mode: makefile -*-
+# RISC-V specific tweaks
+
+VPATH += $(SRC_PATH)/tests/tcg/riscv64
+TESTS += test-div
--
2.31.1
next prev parent reply other threads:[~2021-09-01 2:19 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 2:09 [PULL 00/33] riscv-to-apply queue Alistair Francis
2021-09-01 2:09 ` [PULL 01/33] hw/char: Add config for shakti uart Alistair Francis
2021-09-01 2:09 ` [PULL 02/33] hw/riscv: virt: Move flash node to root Alistair Francis
2021-09-01 2:09 ` [PULL 03/33] target/riscv: Correct a comment in riscv_csrrw() Alistair Francis
2021-09-01 2:09 ` [PULL 04/33] target/riscv: Don't wrongly override isa version Alistair Francis
2021-09-01 2:09 ` [PULL 05/33] target/riscv: Add User CSRs read-only check Alistair Francis
2021-09-01 2:09 ` [PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv() Alistair Francis
2021-09-01 2:09 ` [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp() Alistair Francis
2021-09-01 2:09 ` [PULL 08/33] hw/core/register: Add more 64-bit utilities Alistair Francis
2021-09-01 2:09 ` [PULL 09/33] hw/registerfields: Use 64-bit bitfield for FIELD_DP64 Alistair Francis
2021-09-01 2:09 ` [PULL 10/33] target/riscv: Use tcg_constant_* Alistair Francis
2021-09-01 2:09 ` Alistair Francis [this message]
2021-09-01 2:09 ` [PULL 12/33] target/riscv: Clean up division helpers Alistair Francis
2021-09-01 2:09 ` [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Alistair Francis
2021-09-01 2:09 ` [PULL 14/33] target/riscv: Introduce DisasExtend and new helpers Alistair Francis
2021-09-01 2:09 ` [PULL 15/33] target/riscv: Add DisasExtend to gen_arith* Alistair Francis
2021-09-01 2:09 ` [PULL 16/33] target/riscv: Remove gen_arith_div* Alistair Francis
2021-09-01 2:09 ` [PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu Alistair Francis
2021-09-01 2:09 ` [PULL 18/33] target/riscv: Move gen_* helpers for RVM Alistair Francis
2021-09-01 2:09 ` [PULL 19/33] target/riscv: Move gen_* helpers for RVB Alistair Francis
2021-09-01 2:09 ` [PULL 20/33] target/riscv: Add DisasExtend to gen_unary Alistair Francis
2021-09-01 2:09 ` [PULL 21/33] target/riscv: Use DisasExtend in shift operations Alistair Francis
2021-09-01 2:09 ` [PULL 22/33] target/riscv: Use extracts for sraiw and srliw Alistair Francis
2021-09-01 2:09 ` [PULL 23/33] target/riscv: Use get_gpr in branches Alistair Francis
2021-09-01 2:09 ` [PULL 24/33] target/riscv: Use {get, dest}_gpr for integer load/store Alistair Francis
2021-09-01 2:09 ` [PULL 25/33] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation Alistair Francis
2021-09-01 2:09 ` [PULL 26/33] target/riscv: Fix hgeie, hgeip Alistair Francis
2021-09-01 2:09 ` [PULL 27/33] target/riscv: Reorg csr instructions Alistair Francis
2021-09-01 2:09 ` [PULL 28/33] target/riscv: Use {get,dest}_gpr for RVA Alistair Francis
2021-09-01 2:09 ` [PULL 29/33] target/riscv: Use gen_shift_imm_fn for slli_uw Alistair Francis
2021-09-01 2:09 ` [PULL 30/33] target/riscv: Use {get,dest}_gpr for RVF Alistair Francis
2021-09-01 2:09 ` [PULL 31/33] target/riscv: Use {get,dest}_gpr for RVD Alistair Francis
2021-09-01 2:09 ` [PULL 32/33] target/riscv: Tidy trans_rvh.c.inc Alistair Francis
2021-09-01 2:09 ` [PULL 33/33] target/riscv: Use {get,dest}_gpr for RVV Alistair Francis
2021-09-01 9:56 ` [PULL 00/33] riscv-to-apply queue Peter Maydell
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