From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 4/4] target/arm: Optimize MVE VNEG, VABS
Date: Thu, 2 Sep 2021 16:09:10 +0100 [thread overview]
Message-ID: <20210902150910.15748-5-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210902150910.15748-1-peter.maydell@linaro.org>
Optimize the MVE VNEG and VABS insns by using TCG
vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-mve.c | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 5bc5a3a2063..32c5ff6ea06 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -500,7 +500,8 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
return true;
}
-static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
+static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn,
+ GVecGen2Fn vecfn)
{
TCGv_ptr qd, qm;
@@ -514,16 +515,25 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
return true;
}
- qd = mve_qreg_ptr(a->qd);
- qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qm);
- tcg_temp_free_ptr(qd);
- tcg_temp_free_ptr(qm);
+ if (vecfn && s->mve_no_pred) {
+ vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), 16, 16);
+ } else {
+ qd = mve_qreg_ptr(a->qd);
+ qm = mve_qreg_ptr(a->qm);
+ fn(cpu_env, qd, qm);
+ tcg_temp_free_ptr(qd);
+ tcg_temp_free_ptr(qm);
+ }
mve_update_eci(s);
return true;
}
-#define DO_1OP(INSN, FN) \
+static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
+{
+ return do_1op_vec(s, a, fn, NULL);
+}
+
+#define DO_1OP_VEC(INSN, FN, VECFN) \
static bool trans_##INSN(DisasContext *s, arg_1op *a) \
{ \
static MVEGenOneOpFn * const fns[] = { \
@@ -532,13 +542,15 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
gen_helper_mve_##FN##w, \
NULL, \
}; \
- return do_1op(s, a, fns[a->size]); \
+ return do_1op_vec(s, a, fns[a->size], VECFN); \
}
+#define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL)
+
DO_1OP(VCLZ, vclz)
DO_1OP(VCLS, vcls)
-DO_1OP(VABS, vabs)
-DO_1OP(VNEG, vneg)
+DO_1OP_VEC(VABS, vabs, tcg_gen_gvec_abs)
+DO_1OP_VEC(VNEG, vneg, tcg_gen_gvec_neg)
DO_1OP(VQABS, vqabs)
DO_1OP(VQNEG, vqneg)
DO_1OP(VMAXA, vmaxa)
--
2.20.1
next prev parent reply other threads:[~2021-09-02 15:16 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 15:09 [PATCH 0/4] target/arm: Use TCG vector ops for MVE Peter Maydell
2021-09-02 15:09 ` [PATCH 1/4] target/arm: Add TB flag for "MVE insns not predicated" Peter Maydell
2021-09-03 13:57 ` Richard Henderson
2021-09-03 14:17 ` Peter Maydell
2021-09-03 15:28 ` Richard Henderson
2021-09-03 16:30 ` Peter Maydell
2021-09-07 14:11 ` Richard Henderson
2021-09-07 14:22 ` Richard Henderson
2021-09-10 16:00 ` Peter Maydell
2021-09-12 12:48 ` Richard Henderson
2021-09-09 13:46 ` Peter Maydell
2021-09-10 6:46 ` Richard Henderson
2021-09-10 9:30 ` Peter Maydell
2021-09-10 13:08 ` Richard Henderson
2021-09-09 14:53 ` Peter Maydell
2021-09-02 15:09 ` [PATCH 2/4] target/arm: Optimize MVE logic ops Peter Maydell
2021-09-02 16:19 ` Philippe Mathieu-Daudé
2021-09-03 13:58 ` Richard Henderson
2021-09-02 15:09 ` [PATCH 3/4] target/arm: Optimize MVE arithmetic ops Peter Maydell
2021-09-02 16:20 ` Philippe Mathieu-Daudé
2021-09-03 13:59 ` Richard Henderson
2021-09-02 15:09 ` Peter Maydell [this message]
2021-09-02 16:21 ` [PATCH 4/4] target/arm: Optimize MVE VNEG, VABS Philippe Mathieu-Daudé
2021-09-03 14:00 ` Richard Henderson
2021-09-03 15:14 ` [PATCH 0/4] target/arm: Use TCG vector ops for MVE Richard Henderson
2021-09-03 15:20 ` Peter Maydell
2021-09-03 15:36 ` Richard Henderson
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