From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>,
richard.henderson@linaro.org, groug@kaod.org,
qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br,
david@gibson.dropbear.id.au
Subject: [PATCH v3 00/15] PMU-EBB support for PPC64 TCG
Date: Fri, 3 Sep 2021 17:31:01 -0300 [thread overview]
Message-ID: <20210903203116.80628-1-danielhb413@gmail.com> (raw)
Hi,
This version contains changes suggested by David and Matheus. No big
design changes were made.
Changes from v2:
- former patch 1: merged into patch 2 (former 3)
- patches 1 and 2 (former 2 and 3):
* no more intermediate write reg functions that will replaced shortly after
* do not name specialized write callbacks with '_generic'
* put the read/write MMCR0 ureg bits in a macro
- patch 3 (former 4):
* do not call 'helper_store_mmcr0' in spr_write_MMCR0_ureg
- patch 4 (former 5):
* use extract64 when extracting MMCR1 events
- patch 5 (former 6):
* MMCR0_FC is now represented in a DisasContext flag to avoid poking into
registers before calling the instruction count helper
- patch 6 (former 7):
* writing SPR_CTRL now forces a new translation block
- patch 8 (former 9):
* rename device_tree rfebb format and argument
* crop EBBRR when !msr_is_64bit
* put the helper inside an "#if defined(TARGET_PPPC64)"
* use gen_invalid() when CONFIG_USER_ONLY
- v2 link: https://lists.gnu.org/archive/html/qemu-devel/2021-08/msg04062.html
Daniel Henrique Barboza (13):
target/ppc: add user write access control for PMU SPRs
target/ppc: PMU basic cycle count for pseries TCG
target/ppc/power8_pmu.c: enable PMC1-PMC4 events
target/ppc: PMU: add instruction counting
target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event
target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits
PPC64/TCG: Implement 'rfebb' instruction
target/ppc/excp_helper.c: EBB handling adjustments
target/ppc/power8_pmu.c: enable PMC1 counter negative overflow
target/ppc/power8_pmu.c: cycles overflow with all PMCs
target/ppc: PMU: insns counter negative overflow support
target/ppc/translate: PMU: handle setting of PMCs while running
target/ppc/power8_pmu.c: handle overflow bits when PMU is running
Gustavo Romero (2):
target/ppc: add user read functions for MMCR0 and MMCR2
target/ppc: PMU Event-Based exception support
hw/ppc/spapr_cpu_core.c | 6 +
target/ppc/cpu.h | 61 +++-
target/ppc/cpu_init.c | 38 +-
target/ppc/excp_helper.c | 92 +++++
target/ppc/helper.h | 4 +
target/ppc/helper_regs.c | 6 +
target/ppc/insn32.decode | 5 +
target/ppc/meson.build | 1 +
target/ppc/power8_pmu.c | 470 +++++++++++++++++++++++++
target/ppc/power8_pmu.h | 25 ++
target/ppc/spr_tcg.h | 9 +-
target/ppc/translate.c | 214 ++++++++++-
target/ppc/translate/branch-impl.c.inc | 33 ++
13 files changed, 942 insertions(+), 22 deletions(-)
create mode 100644 target/ppc/power8_pmu.c
create mode 100644 target/ppc/power8_pmu.h
create mode 100644 target/ppc/translate/branch-impl.c.inc
--
2.31.1
next reply other threads:[~2021-09-03 20:36 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-03 20:31 Daniel Henrique Barboza [this message]
2021-09-03 20:31 ` [PATCH v3 01/15] target/ppc: add user read functions for MMCR0 and MMCR2 Daniel Henrique Barboza
2021-09-07 1:27 ` David Gibson
2021-09-22 11:23 ` Matheus K. Ferst
2021-09-22 21:10 ` Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 02/15] target/ppc: add user write access control for PMU SPRs Daniel Henrique Barboza
2021-09-07 1:38 ` David Gibson
2021-09-23 14:39 ` Daniel Henrique Barboza
2021-09-27 5:08 ` David Gibson
2021-09-27 23:05 ` Daniel Henrique Barboza
2021-10-07 1:17 ` David Gibson
2021-09-03 20:31 ` [PATCH v3 03/15] target/ppc: PMU basic cycle count for pseries TCG Daniel Henrique Barboza
2021-09-07 1:48 ` David Gibson
2021-09-22 11:24 ` Matheus K. Ferst
2021-09-24 14:41 ` Daniel Henrique Barboza
2021-09-24 18:34 ` Matheus K. Ferst
2021-09-24 19:05 ` Daniel Henrique Barboza
2021-09-27 5:04 ` David Gibson
2021-09-03 20:31 ` [PATCH v3 04/15] target/ppc/power8_pmu.c: enable PMC1-PMC4 events Daniel Henrique Barboza
2021-09-07 1:50 ` David Gibson
2021-09-03 20:31 ` [PATCH v3 05/15] target/ppc: PMU: add instruction counting Daniel Henrique Barboza
2021-09-07 1:57 ` David Gibson
2021-09-21 21:11 ` Daniel Henrique Barboza
2021-09-27 4:59 ` David Gibson
2021-09-03 20:31 ` [PATCH v3 06/15] target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 07/15] target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 08/15] PPC64/TCG: Implement 'rfebb' instruction Daniel Henrique Barboza
2021-09-09 11:47 ` Matheus K. Ferst
2021-09-22 19:41 ` Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 09/15] target/ppc: PMU Event-Based exception support Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 10/15] target/ppc/excp_helper.c: EBB handling adjustments Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 11/15] target/ppc/power8_pmu.c: enable PMC1 counter negative overflow Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 12/15] target/ppc/power8_pmu.c: cycles overflow with all PMCs Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 13/15] target/ppc: PMU: insns counter negative overflow support Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 14/15] target/ppc/translate: PMU: handle setting of PMCs while running Daniel Henrique Barboza
2021-09-03 20:31 ` [PATCH v3 15/15] target/ppc/power8_pmu.c: handle overflow bits when PMU is running Daniel Henrique Barboza
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