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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id f17sm3959699wrt.63.2021.09.04.16.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Sep 2021 16:56:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 13/24] target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu Date: Sun, 5 Sep 2021 01:55:31 +0200 Message-Id: <20210904235542.1092641-14-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210904235542.1092641-1-f4bug@amsat.org> References: <20210904235542.1092641-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , Warner Losh , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 2 ++ target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 ++----------- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..40401c33b72 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -355,8 +355,10 @@ struct MicroBlazeCPU { }; +#ifndef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +#endif /* !CONFIG_USER_ONLY */ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 72d8f2a0daa..15db277925f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,10 +365,10 @@ static const struct SysemuCPUOps mb_sysemu_ops = { static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, - .cpu_exec_interrupt = mb_cpu_exec_interrupt, .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, .do_unaligned_access = mb_cpu_do_unaligned_access, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 20dbd673136..dd2aecd1d58 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -26,16 +26,6 @@ #if defined(CONFIG_USER_ONLY) -void mb_cpu_do_interrupt(CPUState *cs) -{ - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; - - cs->exception_index = -1; - env->res_addr = RES_ADDR_NONE; - env->regs[14] = env->pc; -} - bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -271,7 +261,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, return paddr; } -#endif bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -289,6 +278,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#endif /* !CONFIG_USER_ONLY */ + void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -- 2.31.1